參數(shù)資料
型號(hào): DS1800
廠商: DALLAS SEMICONDUCTOR
元件分類: 模擬信號(hào)調(diào)理
英文描述: Dual Inverting Log Gain/Attenuator(雙路反相對(duì)數(shù)放大/衰減器)
中文描述: SPECIALTY ANALOG CIRCUIT, PDIP20
封裝: 0.300 INCH, DIP-20
文件頁數(shù): 5/13頁
文件大?。?/td> 96K
代理商: DS1800
DS1800
032098 5/13
Also, if operating in push–button mode, MUTE will be
deactivated if an input is received over any push–button
input. This input, like the push–button inputs, is inter-
nally debounced and requires no external circuitry.
When the device powers up, the first activity on the mute
pin will move the wipers to position 128 or the OUTx end
of the potentiometer(s).
Software muting was discussed in the 3–wire serial con-
trol section. Bits 7 and 15 are reserved for muting each
respective potentiometer. If these bits have value “1”,
the wiper positions of the pot will be transferred to the
mute position. Unlike hardware mute control, software
muting allows the user individual control of each poten-
tiometer. Additionally, the software mute requires that
the complete wiper position setting be rewritten to
establish a non muted position. Note that bits 7 and 15
of the I/O shift register must have value “0” to release the
software mute position.
CASCADE OPERATION
A feature of the DS1800 is the ability to control multiple
devices from a single processor. Multiple DS1800’s can
be linked or daisy chained as shown in Figure 8. As a
data bit is entered into the I/O shift register of the
DS1800, a data bit will appear at the C
OUT
output after a
maximum delay of 50 nanoseconds.
The C
OUT
output of the DS1800 can be used to drive the
D input of another DS1800. When connecting multiple
devices, the total number of bits sent is always 16 times
the number of DS1800’s is the daisy chain.
An optional feedback resistor can be placed between
the C
OUT
terminal of the last device and the D input of
the first DS1800, thus allowing the controlling processor
to circularly clock data through the daisy chain. The
value of the feedback or isolation resistor should be in
the range from 2K to 20K
.
When reading data via the C
OUT
pin and the isolation
resistor, the D input is left floating by the reading device.
When RST is driven high, bit–0 is present on the C
OUT
pin, which is fed back to the D pin through the isolation
resistor. When the CLK input transitions low to high,
bit–0 is loaded into the first position of the I/O shift regis-
ter and bit 1 becomes present on C
OUT
and D of the next
device. After 16 bits (or 16 times the number of
DS1800s in the daisy chain), the data has shifted com-
pletely around and back to its original position. When
RST transitions to the low state to end data transfer, the
value (the same as before the read occurred is loaded
into the wiper–0 and wiper–1 registers.
相關(guān)PDF資料
PDF描述
DS1801 Dual Audio Taper Potentiometer(雙路音頻抽頭電位器)
DS1802 Dual Audio Taper Potentiometer with Push Button Control(帶按鈕控制的雙路音頻抽頭電位器)
DS1803 Addressable Dual Digital Potentiometer(可尋址雙路數(shù)字電位器)
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DS1801E 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Dual Audio Taper Potentiometer
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