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參數(shù)資料
| 型號(hào)： | DS1647P |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | Nonvolatile Timekeeping RAM(非易失性計(jì)時(shí)RAM) |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, DMA34 |
| 封裝： | POWERCAP MODULE-34 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大小： | 131K |
| 代理商： | DS1647P |
DS1647/DS1647P
031798 4/12
DS1647 REGISTER MAP - BANK1
Table 2
ADDRESS
DATA
FUNCTION
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
7FFFF
–
–
–
–
–
–
–
–
YEAR
00–99
7FFFE
X
X
X
–
–
–
–
–
MONTH
01–12
7FFFD
X
X
–
–
–
–
–
–
DATE
01–31
7FFFC
X
FT
X
X
X
–
–
–
DAY
01–07
7FFFB
X
X
–
–
–
–
–
–
HOUR
00–23
7FFFA
X
–
–
–
–
–
–
–
MINUTES
00–59
7FFF9
OSC
–
–
–
–
–
–
–
SECONDS
00–59
7FFF8
W
R
X
X
X
X
X
X
CONTROL
A
OSC = STOP BIT
W
= WRITE BIT
R
X
=
=
READ BIT
UNUSED
FT =
FREQUENCY TEST
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1647 is in the read mode whenever WE (write
enable) is high, CE (chip enable) is low. The device ar-
chitecture allows ripple–through access to any of the
address locations in the NV SRAM. Valid data will be
available at the DQ pins within t
AA
after the last address
input is stable, providing that the CE and OE access
times and states are satisfied. If CE or OE access times
are not met, valid data will be available at the latter of
chip enable access (t
CEA
) or at output enable access
time (t
OEA
). The state of the data input/output pins (DQ)
is controlled by CE and OE. If the outputs are activated
before t
AA
, the data lines are driven to an intermediate
state until t
AA
. If the address inputs are changed while
CE and OE remain valid, output data will remain valid for
output data hold time (t
OH
) but will then go indeterminate
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1647 is in the write mode whenever WE and CE
are in their active state. The start of a write is referenced
to the latter occurring high to low transition of WE and
CE. The addresses must be held valid throughout the
cycle. CE or WE must return inactive for a minimum of
t
WR
prior to the initiation of another read or write cycle.
Data in must be valid t
DS
prior to the end of write and re-
main valid for t
DH
afterward. In a typical application, the
OE signal will be high during a write cycle. However,
OE can be active provided that care is taken with the
data bus to avoid bus contention. If OE is low prior to
WE transitioning low the data bus can become active
with read data defined by the address inputs. A low tran-
sition on WE will then disable the outputs t
WEZ
after WE
goes active.
DATA RETENTION MODE
When V
CCI
is within nominal limits (V
CC
> 4.5 volts) the
DS1647 can be accessed as described above with read
or write cycles. However, when V
CC
is below the pow-
er–fail point V
PF
(point at which write protection occurs)
the internal clock registers and RAM is blocked from ac-
cess. This is accomplished internally by inhibiting ac-
cess via the CE signal. At this time the power–fail output
signal (PFO) will be driven active low and will remain
active until V
CC
returns to nominal levels. When V
CC
falls below the level of the internal battery supply, power
input is switched from the V
CC
pin to the internal battery
and clock activity, RAM, and clock data are maintained
from the battery until V
CC
is returned to nominal level.
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