
DS1647/DS1647P
031798 2/12
DESCRIPTION
The DS1647 is a 512K x 8 nonvolatile static RAM with a
full function real time clock which are both accessible in
a Byte–wide format. The nonvolatile time keeping RAM
is function equivalent to any JEDEC standard 512K x 8
SRAM. The device can also be easily substituted for
ROM, EPROM and EEPROM, providing read/write
nonvolatility and the addition of the real time clock func-
tion. The real time clock information resides in the eight
uppermost RAM locations. The RTC registers contain
year, month, date, day, hours, minutes, and seconds
data in 24 hour BCD format. Corrections for the day of
the month and leap year are made automatically. The
RTC clock registers are double buffered to avoid access
of incorrect data that can occur during clock update
cycles. The double buffered system also prevents time
loss as the timekeeping countdown continues unabated
by access to time register data. The DS1647 also con-
tains its own power–fail circuitry which deselects the de-
vice when the V
CC
supply is in an out of tolerance condi-
tion. This feature prevents loss of data from
unpredictable system operation brought on by low V
CC
as errant access and update cycles are avoided.
PACKAGES
The DS1647 is available in two packages (32–pin DIP
module and 34–pin PowerCap module). The 32–pin
Dip style module integrated the crystal, lithium energy
source, and silicon all in one package. The 34–pin Pow-
erCap Module Board is designed with contacts for con-
nection to a separate PowerCap (DS9034PCX) that
contains the crystal and battery. The design allows the
PowerCap to be mounted on top of the DS1647P after
the completion of the surface mount process. Mounting
the PowerCap after the surface mount process pre-
vents damage to the crystal and battery due to high tem-
peratures required for solder reflow. The PowerCap is
keyed to prevent reverse insertion. The PowerCap
Module Board and PowerCap are ordered separately
and shipped in separate containers. The part number
for the PowerCap is DS9034PCX.
CLOCK OPERATIONS–READING THE
CLOCK
While the double buffered register structure reduces the
chance of reading incorrect data, internal updates to the
DS1647 clock registers should be halted before clock
data is read to prevent reading of data in transition.
However, halting the internal clock register updating
process does not affect clock accuracy. Updating is
halted when a one is written into the read bit, the seventh
most significant bit in the control register. As long as a
one remains in that position, updating is halted. After a
halt is issued, the registers reflect the count, that is day,
date, and time that was current at the moment the halt
command was issued. However, the internal clock reg-
isters of the double buffered system continue to update
so that the clock accuracy is not affected by the access
of data. All of the DS1647 registers are updated simul-
taneously after the clock status is reset. Updating is
within a second after the read bit is written to zero.
BLOCK DIAGRAM DS1647
Figure 1
COSCICHAIN
POWER MONITOR,
SWITCHING, AND
WRITE PROTECTION
V
CC
POWER GOOD
CLOCK
REGISTERS
512K X 8 NV SRAM
CE
WE
A0–A18
DQ0–DQ7
32.768 KHz
+
OE
PFO
V
BAT