參數(shù)資料
型號(hào): DS1500YN
廠商: Maxim Integrated Products
文件頁數(shù): 6/20頁
文件大小: 0K
描述: IC RTC Y2KC W/NV CTRL 5V 32-DIP
標(biāo)準(zhǔn)包裝: 13
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,NVSRAM,方波輸出,監(jiān)視計(jì)時(shí)器,Y2K
存儲(chǔ)容量: 256B
時(shí)間格式: HH:MM:SS(24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 2.5 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 32-DIP 模塊(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 32-EDIP
包裝: 管件
DS1500 Y2K Watchdog RTC with Nonvolatile Control
14 of 20
The alarm can be programmed to activate on a specific day of the month, day of the week, or repeat every day,
hour, minute, or second. It can also be programmed to go off while the DS1500 is in the battery-backed state of
operation to serve as a system wakeup. Alarm mask bits AM1 to AM4 control the alarm mode. Table 3 shows the
possible settings. Configurations not listed in the table default to the once-per-second mode to notify the user of an
incorrect alarm setting. When the RTC register values match alarm register settings, the time-of-day/date alarm
flag TDF bit is set to 1. Once the TDF flag is set, the TIE bit enables the alarm to activate the IRQ pin. The TPE bit
enables the alarm flag to activate the PWR pin. The alarm functions on VCC, VBAT, and VBAUX.
Table 3. Alarm Mask Bits
DY/DT
AM4
AM3
AM2
AM1
ALARM RATE
X
1
Once per second
X
1
0
When seconds match
X
1
0
When minutes and seconds match
X
1
0
When hours, minutes, and seconds match
0
When date, hours, minutes, and seconds match
1
0
When day, hours, minutes, and seconds match
CONTROL REGISTERS
The controls and status information for the DS1500 features are maintained in the following register bits.
Month Register (05h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EOSC
E32K
BB32
10 Month
Month
EOSC,
Oscillator Start/Stop Bit (05h Bit 7)
This bit when set to logic 0 starts the oscillator. When this bit is set to logic 1, the oscillator is stopped. This bit is
automatically set to logic 0 by the internal power-on reset when power is applied and VCC rises above the power-fail
voltage.
E32K,
Enable 32.768kHz Output (05h Bit 6)
This bit, when written to 0, enables the 32.768 kHz oscillator frequency to be output on the SQW pin if the oscillator
is running. This bit is automatically set to logic 0 by the internal power-on reset when power is applied and VCC
rises above the power-fail voltage.
BB32, Battery Backup 32kHz Enable Bit (05h Bit 5)
When the BB32 bit is written to 1, it enables a 32kHz signal to be output on the SQW pin while the part is in
battery-backup mode, if voltage is applied to VBAUX.
AM1 to AM4, Alarm Mask Bits (08h Bit 7; 09h Bit 7; 0Ah Bit 7; 0Bh Bit 7)
Bit 7 of registers 08h to 0Bh contains an alarm mask bit, AM1 to AM4. These bits, in conjunction with the TIE
described later, allow the IRQ output to be activated for a matched-alarm condition. The alarm can be programmed
to activate on a specific day of the month, day of the week, or repeat every day, hour, minute, or second. Table 3
shows the possible settings for AM1 to AM4 and the resulting alarm rates. Configurations not listed in the table
default to the once-per-second mode to notify the user of an incorrect alarm setting.
DY/DT, Day/Date Bit (0Bh Bit 6)
The DY/DT bit controls whether the alarm value stored in bits 0 to 5 of 0Bh reflects the day of the week or the date
of the month. If DY/DT is written to a 0, the alarm is the result of a match with the date of the month. If DY/DT is
written to a 1, the alarm is the result of a match with the day of the week.
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