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參數(shù)資料
| 型號： | DS1500YN |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC Y2KC W/NV CTRL 5V 32-DIP |
| 標準包裝： | 13 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，NVSRAM，方波輸出，監(jiān)視計時器，Y2K |
| 存儲容量： | 256B |
| 時間格式： | HH:MM:SS（24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP 模塊（0.600"，15.24mm） |
| 供應商設備封裝： | 32-EDIP |
| 包裝： | 管件 |
DS1500 Y2KC Watchdog RTC with Nonvolatile Control
11 of 20
DETAILED DESCRIPTION
The RTC registers are double buffered into an internal and external set. The user has direct access to the external
set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access
static data. When the crystal oscillator is turned on, the internal set of registers are continuously updated; this
occurs regardless of external register settings to guarantee that accurate RTC information is always maintained.
The DS1500 contains its own power-fail circuitry that automatically deselects the device when the VCCI supply falls
below a power-fail trip point. This feature provides a high degree of data security during unpredictable system
operation caused by low VCCI levels. An external SRAM can be made nonvolatile by using the VCCO and CEO pins.
Nonvolatile control of the external SRAM is analogous to that of the RTC registers. When VCCI slews down during a
power fail, CEO is driven to an inactive level regardless of CEI. This write protection occurs when VCCI is less than
the power-fail trip point.
The DS1500 has interrupt (IRQ), power control (PWR), and reset (RST) outputs that can be used to control CPU
activity. The IRQ interrupt or RST outputs can be invoked as the result of a time-of-day alarm, CPU watchdog
alarm, or a kickstart signal. The DS1500 power-control circuitry allows the system to be powered on by an external
stimulus, such as a keyboard or by a time and date (wakeup) alarm. The PWR output pin can be triggered by one
or either of these events, and can be used to turn on an external power supply. The PWR pin is under software
control, so that when a task is complete, the system power can then be shut down. The DS1500 power-on reset
can be used to detect a system power-down or failure and hold the CPU in a safe reset state until normal power
returns and stabilizes; the RST output is used for this function.
The DS1500 is a clock/calendar chip with the features described above. An external crystal and battery are the
only components required to maintain time-of-day and memory status in the absence of power..
Table 1. RTC Operating Modes
VCCI
CS
OE
WE
DQ0–DQ7
A0–A4
MODE
POWER
VCCI > VPF
V
IH
X
High-Z
X
Deselect
Standby
V
IL
X
V
IL
D
IN
A
IN
Write
Active
V
IL
V
IL
V
IH
D
OUT
A
IN
Read
Active
V
IL
V
IH
V
IH
High-Z
A
IN
Read
Active
VSO < VCCI < VPF
X
High-Z
X
Deselect
CMOS Standby
VCCI < VSO < VPF
X
High-Z
X
Data Retention
Battery Current
DATA READ MODE
The DS1500 is in read mode whenever CS (chip select) and OE (output enable) are low and WE (write enable) is
high. The device architecture allows ripple-through access to any valid address location. Valid data is available at
the DQ pins within t
AA (address access) after the last address input is stable, provided that CS and OE access
times are satisfied. If CS or OE access times are not met, valid data is available at the latter of chip-enable access
(t
CSA) or at output-enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CS and
OE
. If the outputs are activated before t
AA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while CS and OE remain valid, output data remains valid for output-data hold time (t
OH) but then
goes indeterminate until the next address access (Table 1).
DATA WRITE MODE
The DS1500 is in write mode whenever CS and WE are in their active state. The start of a write is referenced to the
latter occurring transition of CS or WE. The addresses must be held valid throughout the cycle. CS or WE must
return inactive for a minimum of t
WR prior to the initiation of a subsequent read or write cycle. Data in must be valid
t
DS prior to the end of the write and remain valid for tDH afterward. In a typical application, the OE signal is high
during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus
contention. If OE is low prior to a high-to-low transition on WE, the data bus can become active with read data
defined by the address inputs. A low transition on WE then disables the outputs t
WEZ after WE goes active (Table 1).
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