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參數(shù)資料
| 型號： | DS1500YN |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 0K |
| 描述： | IC RTC Y2KC W/NV CTRL 5V 32-DIP |
| 標準包裝： | 13 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，NVSRAM，方波輸出，監(jiān)視計時器，Y2K |
| 存儲容量： | 256B |
| 時間格式： | HH:MM:SS（24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | 并聯(lián) |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 2.5 V ~ 3.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-DIP 模塊（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 32-EDIP |
| 包裝： | 管件 |
DS1500 Y2KC Watchdog RTC with Nonvolatile Control
12 of 20
DATA RETENTION MODE
The DS1500 is fully accessible and data can be written and read only when VCCI is greater than VPF. However,
when VCCI falls below the power-fail point VPF (point at which write protection occurs) the internal clock registers
and SRAM are blocked from any access. While in the data retention mode, all inputs are don’t cares and outputs
go to a high-Z state, with the exception of VCCO, CEO, and with the possible exception of KS, PWR, SQW, and RST.
CEO
is forced high. If VPF is less than VBAT and VBAUX, the device power is switched from VCCI to the greater of VBAT
and VBAUX when VCCI drops below VPF. If VPF is greater than VBAT and VBAUX, the device power and VCCO are
switched from VCCI to the larger of VBAT and VBAUX when VCCI drops below the larger of VBAT and VBAUX. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels (Table 1). If the
square-wave and battery-backup 32kHz functions are enabled, VBAUX always provides power for the square-wave
output, when the device is in battery-backup mode. All control, data, and address signals must be no more than
0.3V above VCCI.
AUXILIARY BATTERY
The VBAUX input is provided to supply power from an auxiliary battery for the DS1500 kickstart and square-wave
output features in the absence of VCCI. This power source must be available to use these auxiliary features when
no VCCI is applied to the device.
This auxiliary battery can be used as the primary backup power source for maintaining the clock/calendar and
external SRAM. This occurs if the VBAT pin is at a lower voltage than VBAUX. If the DS1500 is to be backed-up using
a single battery with the auxiliary features enabled, then VBAUX should be used and connected to VBAT. If VBAUX is
not to be used, it should be grounded.
POWER-ON RESET
A temperature-compensated comparator circuit monitors the level of V
CCI. When VCCI falls to the power-fail trip
point, the RST signal (open drain) is pulled low. When V
CCI returns to nominal levels, the RST signal continues to be
pulled low for a period of tREC. The power-on reset function is independent of the RTC oscillator and therefore
operational whether or not the oscillator is enabled.
TIME AND DATE OPERATION
The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the RTC
registers. The time and date are set or initialized by writing the appropriate register bytes. The contents of the time
and date registers are in the binary-coded decimal (BCD) format. Hours are in 24-hour mode. The day-of-week
register increments at midnight. Values that correspond to the day of week are user-defined, but must be
sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in
undefined operation.
READING THE CLOCK
When reading the clock and calendar data, it is possible to access the registers while an update (once per second)
occurs. There are three ways to avoid using invalid time and date data.
The first method uses the transfer enable (TE) bit in the control B register. Transfers are halted when a 0 is written
to the TE bit. Setting TE to 0 halts updates to the user-accessible registers, while allowing the internal registers to
advance. After the registers are read, the TE bit should be written to 1. TE must be kept at 1 for at least 366μs to
ensure a user register update.
The time and date registers can be read and stored in temporary variables. The time and date registers are then
read again, and compared to the first values. If the values do not match, the time and date registers should be read
a third time and compared to the previous values. This should be done until two consecutive reads of the time and
date registers match. The TE bit should always be enabled when using this method for reading the time and date,.
The third method of reading the time and date uses the alarm function. The alarm can be configured to activate
once per second, and the time-of-day alarm-interrupt enable bit (TIE) is enabled. The TE bit should always be
enabled. When the IRQ pin goes active, the time and date information does not change until the next update.
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