參數(shù)資料
型號(hào): DS14287
廠商: DALLAS SEMICONDUCTOR
元件分類(lèi): XO, clock
英文描述: Real Time Clock with NV RAM Control(帶非易失性RAM控制的實(shí)時(shí)時(shí)鐘)
中文描述: 1 TIMER(S), REAL TIME CLOCK, PDIP24
封裝: MODULE, DIP-24
文件頁(yè)數(shù): 6/23頁(yè)
文件大?。?/td> 170K
代理商: DS14287
DS14285/DS14287
022798 6/23
AD0–AD7 (Multiplexed Bidirectional Address/Data
Bus)
– Multiplexed buses save pins because address
information and data information time share the same
signal paths. The addresses are present during the first
portion of the bus cycle and the same pins and signal
paths are used for data in the second portion of the cycle.
Address/data multiplexing does not slow the access time
of the DS14285/DS14287 since the bus change from
address to data occurs during the internal RAM access
time. Addresses must be valid prior to the falling edge of
AS/ALE, at which time the DS14285/DS14287 latches
the address from AD0 to AD6. Valid write data must be
present and held stable during the latter portion of the DS
or WR pulses. In a read cycle the DS14285/DS14287
outputs 8 bits of data during the latter portion of the DS or
RD pulses. The read cycle is terminated and the bus
returns to a high impedance state as DS transitions low in
the case of Motorola timing or as RD transitions high in
the case of Intel timing.
MOT (Mode Select)
The MOT pin offers the flexibility
to choose between to bus types. When connected to
V
CC
, Motorola bus timing is selected. When connected
to GND or left disconnected, Intel bus timing is selected.
The pin has an internal pull–down resistance of approxi-
mately 20 K
. This pin is on the DS14285Q only.
AS (Address Strobe Input) –
A positive going address
strobe pulse serves to demultiplex the bus. The falling
edge of AS/ALE causes the address to be latched within
the DS14285/DS14287.
DS (Data Strobe or Read Input)
For the DS14285Q
the DS/RD pin has two modes of operation depending
on the level of the MOT pin. When the MOT pin is con-
nected to V
CC
, Motorola bus timing is selected. In this
mode DS is a positive pulse during the latter portion of
the bus cycle and is called Data Strobe. During read
cycles, DS signifies the time that the DS14285Q is to
drive the bidirectional bus. In write cycles the trailing
edge of DS causes the DS14285Q to latch the written
data. When the MOT pin is connected to GND, Intel bus
timing is selected. In this mode the DS pin is called
Read(RD). RD identifies the time period when the
DS14285Q drives the bus with read data. The RD sig-
nal is the same definition as the Output Enable (OE) sig-
nal on a typical memory.
The DS14285, DS14285S and DS14287 do not have a
MOT pin and therefore operate only in Intel bus timing
mode.
R/W (Read/Write Input) –
The R/W pin also has two
modes of operation. When the MOT pin is connected to
V
CC
for Motorola timing, R/W is at a level which indicates
whether the current cycle is a read or write. A read cycle
is indicated with a high level on R/W while DS is high. A
write cycle is indicated when R/W is low during DS.
When the MOT pin is connected to GND for Intel timing,
the R/W signal is an active low signal called WR. In this
mode the R/W pin has the same meaning as the Write
Enable signal (WE) on generic RAMs.
CS (Chip Select Input)
The Chip Select signal must
be
asserted
low
for
DS14285/DS14287 to be accessed. CS must be kept in
the active state during DS for Motorola timing and during
RD and WR for Intel timing. Bus cycles which take
place without asserting CS will latch addresses but no
access will occur. When V
CC
is below 4.25 volts, the
DS14285/DS14287 internally inhibits access cycles by
internally disabling the CS input. This action protects
both the real time clock data and RAM data during
power outages.
a
bus
cycle
in
the
IRQ (Interrupt Request Output)
The IRQ pin is an
active low output of the DS14285/DS14287 that can be
used as an interrupt input to a processor. The IRQ output
remains low as long as the status bit causing the interrupt
is present and the corresponding interrupt-enable bit is
set. To clear the IRQ pin the processor program normally
reads the C register. The RESET pin also clears pending
interrupts.
When no interrupt conditions are present, the IRQ level is
in the high impedance state. Multiple interrupting devices
can be connected to an IRQ bus. The IRQ bus is an open
drain output and requires an external pull–up resistor.
RESET (Reset Input) –
The RESET pin has no effect
on the clock, calendar, or RAM. On power-up the
RESET pin can be held low for a time in order to allow
the power supply to stabilize. The amount of time that
RESET is held low is dependent on the application.
However, if RESET is used on power-up, the time
RESET is low should exceed 200 ms to make sure that
the internal timer that controls the DS14285/DS14287
on power-up has timed out. When RESET is low and
V
CC
is above 4.25 volts, the follow ing occurs:
A. Periodic Interrupt Enable (PEI) bit is cleared to
zero.
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