參數(shù)資料
型號(hào): DS14287
廠商: DALLAS SEMICONDUCTOR
元件分類: XO, clock
英文描述: Real Time Clock with NV RAM Control(帶非易失性RAM控制的實(shí)時(shí)時(shí)鐘)
中文描述: 1 TIMER(S), REAL TIME CLOCK, PDIP24
封裝: MODULE, DIP-24
文件頁(yè)數(shù): 12/23頁(yè)
文件大?。?/td> 170K
代理商: DS14287
DS14285/DS14287
022798 12/23
SQWE
When the Square Wave Enable (SQWE) bit is set to a
one, a square wave signal at the frequency set by the
rate-selection bits RS3 through RS0 is driven out on a
SQW pin. When the SQWE bit is set to zero, the SQW
pin is held low; the state of SQWE is cleared by the
RESET pin. SQWE is a read/write bit.
DM
The Data Mode (DM) bit indicates whether time and cal-
endar information is in binary or BCD format. The DM bit
is set by the program to the appropriate format and can be
read as required. This bit is not modified by internal func-
tions or RESET. A one in DM signifies binary data while a
zero in DM specifies Binary Coded Decimal (BCD) data.
24/12
The 24/12 control bit establishes the format of the hours
byte. A one indicates the 24–hour mode and a zero indi-
cates the 12–hour mode. This bit is read/write and is not
affected by internal functions of RESET.
DSE
The Daylight Savings Enable (DSE) bit is a read/write bit
which enables two special updates when DSE is set to
one. On the first Sunday in April the time increments
from 1:59:59 AM to 3:00:00 AM. On the last Sunday in
October when the time first reaches 1:59:59 AM it
changes to 1:00:00 AM. These special updates do not
occur when the DSE bit is a zero. This bit is not affected
by internal functions or RESET.
REGISTER C
MSB
BIT 7
LSB
BIT 0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
IRQF
PF
AF
UF
0
0
0
0
IRQF
The Interrupt Request Flag (IRQF) bit is set to a one
when one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
That is, IRQF = PF
PIE + AF
AIE + UF
UIE.
Any time the IRQF bit is a one, the IRQ pin is driven low.
All flag bits are cleared after Register C is read by the
program or when the RESET pin is low.
PF
The Periodic Interrupt Flag (PF) is a read-only bit which is
set to a one when an edge is detected on the selected tap
of the divider chain. The RS3 through RS0 bits establish
the periodic rate. PF is set to a one independent of the
state of the PIE bit. When both PF and PIE are ones, the
IRQ signal is active and will set the IRQF bit. The PF bit is
cleared by a RESET or a software read of Register C.
AF
A one in the Alarm Interrupt Flag (AF) bit indicates that
the current time has matched the alarm time. If the AIE
bit is also a one, the IRQ pin will go low and a one will
appear in the IRQF bit. A RESET or a read of Register C
will clear AF.
UF
The Update Ended Interrupt Flag (UF) bit is set after each
update cycle. When the UIE bit is set to one, the one in
UF causes the IRQF bit to be a one which will assert the
IRQ pin. UF is cleared by reading Register C or a RESET.
BIT 0 THROUGH BIT 3
These are unused bits of the status Register C. These
bits always read zero and cannot be written.
REGISTER D
MSB
BIT 7
LSB
BIT 0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
VRT
0
0
0
0
0
0
0
VRT
The Valid RAM and Time (VRT) bit indicates the condi-
tion of the internal battery (the battery connected to the
V
BAT
pin in the case of the DS14285S, DS14285, and
the DS14285Q). This bit is not writable and should
always be a one when read. If a zero is ever present, an
exhausted internal lithium energy source is indicated
and both the contents of the RTC data and RAM data
are questionable. This bit is unaffected by RESET.
BIT 6 THROUGH BIT 0
The remaining bits of Register D are not usable. They can-
not be written and, when read, they will always read zero.
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