
DS14285/DS14287
022798 10/23
PERIODIC INTERRUPT SELECTION
The periodic interrupt will cause the IRQ pin to go to an
active state from once every 500 ms to once every
122
μ
s. This function is separate from the alarm inter-
rupt which can be output from once per second to once
per day. The periodic interrupt rate is selected using the
same Register A bits which select the square wave fre-
quency (see Table 1). Changing the Register A bits
affects both the square wave frequency and the periodic
interrupt output. However, each function has a separate
enable bit in Register B. The SQWE bit controls the
square wave output. Similarly, the periodic interrupt is
enabled by the PIE bit in Register B. The periodic inter-
rupt can be used with software counters to measure
inputs, create output intervals, or await the next needed
software function.
UPDATE CYCLE
The DS14285/DS14287 executes an update cycle once
per second regardless of the SET bit in Register B.
When the SET bit in Register B is set to one, the user
copy of the double buffered time, calendar, and alarm
bytes is frozen and will not update as the time incre-
ments. However, the time countdown chain continues
to update the internal copy of the buffer. This feature
allows time to maintain accuracy independent of read-
ing or writing the time, calendar, and alarm buffers and
also guarantees that time and calendar information is
consistent. The update cycle also compares each
alarm byte with the corresponding time byte and issues
an alarm if a match or if a “don’t care” code is present in
all three positions.
There are three methods that can handle access of the
real time clock that avoid any possibility of accessing
inconsistent time and calendar data. The first method
uses the update–ended interrupt. If enabled, an inter-
rupt occurs after every up date cycle that indicates that
over 999 ms are available to read valid time and date
information. If this interrupt is used, the IRQF bit in Reg-
ister C should be cleared before leaving the interrupt
routine.
A second method uses the update-in-progress bit (UIP)
in Register A to determine if the update cycle is in prog-
ress. The UIP bit will pulse once per second. After the
UIP bit goes high, the update transfer occurs 244
μ
s
later. If a low is read on the UIP bit, the user has at least
244
μ
s before the time/calendar data will be changed.
Therefore, the user should avoid interrupt service rou-
tines that would cause the time needed to read valid
time/calendar data to exceed 244
μ
s.
The third method uses a periodic interrupt to determine
if an update cycle is in progress. The UIP bit in Register
A is set high between the setting of the PF bit in Register
C (see Figure 4). Periodic interrupts that occur at a rate
of greater than t
BUC
allow valid time and date informa-
tion to be reached at each occurrence of the periodic
interrupt. The reads should be complete within 1
(t
PI/2
+ t
BUC
) to ensure that data is not read during the
update cycle.
UPDATE–ENDED AND PERIODIC INTERRUPT RELATIONSHIP
Figure 4
UIP BIT IN
REGISTER A
UF BIT IN
REGISTER B
PF BIT IN
REGISTER C
t
PI
t
PI/2
t
PI/2
t
BUC
t
PI
= Periodic interrupt time interval per Table 1.
t
BUC
= Delay time before update cycle = 244
μ
s.