參數(shù)資料
型號(hào): DS1286
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: XO, clock
英文描述: Watchdog Timekeeper(看門狗計(jì)時(shí)器芯片)
中文描述: 1 TIMER(S), REAL TIME CLOCK, DMA28
封裝: EDIP MODULE-28
文件頁數(shù): 6/12頁
文件大?。?/td> 122K
代理商: DS1286
DS1286
022798 6/12
COMMAND REGISTER
Address location 0B is the Command Register where
mask bits, control bits, and flag bits reside. Bit 0 is the
Time of Day Alarm Flag (TDF). When this bit is set inter-
nally to a logic one, an alarm has occurred. The time of
the alarm can be determined by reading the Time of Day
Alarm registers. However, if the transfer enable bit is set
to logic zero the Time of Day registers may not reflect
the exact time that the alarm occurred. This bit is read
only and writing this register has no effect on the bit.
The bit is reset when any of the Time of Day Alarm regis-
ters are read. Bit 1 is the Watchdog Alarm Flag (WAF).
When this bit is set internally to a logic one, a Watchdog
Alarm has occurred. This bit is read only and writing this
register has no effect on the bit. The bit is reset when
any of the Watchdog Alarm registers are accessed. Bit
2 of the Command Register contains the Time of Day
Alarm Mask Bit (TDM). When this bit is written to a logic
one, the Time of Day Alarm Interrupt Output is deacti-
vated regardless of the value of the Time of Day Alarm
Flag. When TDM is set to logic zero, the Time of Day
Interrupt Output will go to the active state which is deter-
mined by bits 0, 4, 5, and 6 of the Command Register.
Bit 3 of the Command Register contains the Watchdog
Alarm Mask bit (WAM). When this bit is written to a logic
one, the Watchdog Interrupt Output is deactivated re-
gardless of the value in the Watchdog Alarm registers.
When WAM is set to logic zero, the Watchdog Interrupt
Output will go to the active state which is determined by
bits 1, 4, 5, and 6 of the Command Register. These four
bits define how Interrupt Output Pins INTA and INTB
(INTB) will be operated. Bit 4 of the Command Register
determines whether both interrupts will output a pulse or
level when activated. If Bit 4 is set to logic one, the pulse
mode is selected and INTA will sink current for a mini-
mum of 3 ms and then release. Output INTB (INTB) will
either sink or source current for a minimum of 3 ms de-
pending on the level of bit 5. When bit 5 is set to logic
one, the B interrupt will source current. When bit 5 is set
to logic zero, the B interrupt will sink current. Bit 6 of the
Command Register directs which type of interrupt will
be present on interrupt pins INTA or INTB(INTB). When
set to logic one, INTA becomes the Time of Day Alarm
Interrupt pin and INTB(INTB) becomes the Watchdog
Interrupt pin. When bit 6 is set to logic zero, the interrupt
functions are reversed such that the Time of Day Alarm
will be output on INTB(INTB) and the Watchdog Inter-
rupt will be output on INTA. Caution should be exercised
when dynamically setting this bit as the interrupts will be
reversed even if in an active state. Bit 7 of the Command
Register is for Transfer Enable (TE). The function of this
bit is described in the Time of Day registers.
TIME OF DAY ALARM MASK BITS
Figure 3
(3)MINUTES
(5)HOURS
(7)DAYS
1
0
ALARM ONCE PER MINUTE
ALARM WHEN MINUTES MATCH
ALARM WHEN HOURS AND MINUTES MATCH
ALARM WHEN HOURS, MINUTES,
AND DAYS MATCH
1
1
1
1
1
0
0
0
0
0
REGISTER
相關(guān)PDF資料
PDF描述
DS1287A Real Time Clock(實(shí)時(shí)時(shí)鐘)
DS1287 Real Time Clock(實(shí)時(shí)時(shí)鐘)
DS12885 Real Time Clock(實(shí)時(shí)時(shí)鐘)
DS12885Q Real Time Clock(實(shí)時(shí)時(shí)鐘)
DS12885T Real Time Clock(實(shí)時(shí)時(shí)鐘)
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