參數(shù)資料
型號: DS1286
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: XO, clock
英文描述: Watchdog Timekeeper(看門狗計時器芯片)
中文描述: 1 TIMER(S), REAL TIME CLOCK, DMA28
封裝: EDIP MODULE-28
文件頁數(shù): 2/12頁
文件大?。?/td> 122K
代理商: DS1286
DS1286
022798 2/12
month, and year. The date at the end of the month is au-
tomatically adjusted for months with less than 31 days,
including correction for leap year. The Watchdog Time-
keeper operates in either 24 hour or 12 hour format with
an AM/PM indicator. The watchdog timer provides
alarm windows and interval timing between 0.01 sec-
onds and 99.99 seconds. The real time alarm provides
for preset times of up to one week.
OPERATION – READ REGISTERS
The DS1286 executes a read cycle whenever WE
(Write Enable) is inactive (High) and CE (Chip Enable)
and OE (Output Enable) are active (Low). The unique
address specified by the six address inputs (A0–A5) de-
fines which of the 64 registers is to be accessed. Valid
data will be available to the eight data output drivers
within t
ACC
(Access Time) after the last address input
signal is stable, providing that CE and OE access times
are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the
latter occurring signal (CE or OE) and the limiting pa-
rameter is either t
CO
for CE or t
OE
for OE rather than ad-
dress access.
OPERATION – WRITE REGISTERS
The DS1286 is in the write mode whenever the WE
(Write Enable) and CE (Chip Enable) signals are in the
active (Low) state after the address inputs are stable.
The latter occurring falling edge of CE or WE will deter-
mine the start of the write cycle. The write cycle is termi-
nated by the earlier rising edge of CE or WE. All address
inputs must be kept valid throughout the write cycle. WE
must return to the high state for a minimum recovery
state (t
WR
) before another cycle can be initiated. Data
must be valid on the data bus with sufficient Data Set Up
(t
DS
) and Data Hold Time (t
DH
) with respect to the earlier
rising edge of CE or WE. The OE control signal should
be kept inactive (High) during write cycles to avoid bus
contention. However, if the output bus has been en-
abled (CE and OE active), then WE will disable the out-
puts in t
ODW
from its falling edge.
DATA RETENTION
The Watchdog Timekeeper provides full functional ca-
pability when V
CC
is greater than 4.5 volts and write pro-
tects the register contents at 4.25 volts typical. Data is
maintained in the absence of V
CC
without any additional
support circuitry. The DS1286 constantly monitors V
CC
.
Should the supply voltage decay, the Watchdog Time-
keeper will automatically write protect itself and all in-
puts to the registers become “Don’t Care”. Both INTA
and INTB(INTB) are open drain outputs. The two inter-
rupts and the internal clock continue to run regardless of
the level of V
CC
. However, it is important to insure that
the pull–up resistors used with the interrupt pins are
never pulled up to a value which is greater than V
CC
+
0.3V. As V
CC
falls below approximately 3.0 volts, a
power switching circuit turns the lithium energy source
on to maintain the clock, and timer data functionality. It
is also required to insure that during this time (battery
backup mode), the voltage present at INTA and
INTB(INTB) does never exceed 3.0V. At all times the
current on each should not exceed +2.1 mA or –1.0 mA.
However, if the active high mode is selected for
INTB(INTB), this pin will only go high in the presence of
V
CC
. During power–up, when V
CC
rises above approxi-
mately 3.0 volts, the power switching circuit connects
external V
CC
and disconnects the internal lithium ener-
gy source. Normal operation can resume after V
CC
ex-
ceeds 4.5 volts for a period of 150 ms.
WATCHDOG TIMEKEEPER REGISTERS
The Watchdog Timekeeper has 64 registers which are
eight bits wide that contain all of the Timekeeping,
Alarm, Watchdog, Control, and Data information. The
Clock, Calendar, Alarm, and Watchdog registers are
memory locations which contain external (user–acces-
sible) and internal copies of the data. The external co-
pies are independent of internal functions except that
they are updated periodically by the simultaneous trans-
fer of the incremented internal copy (see Figure 1). The
Command Register bits are affected by both internal
and external functions. This register will be discussed
later. The 50 bytes of RAM registers can only be ac-
cessed from the external address and data bus. Regis-
ters 0, 1, 2, 4, 6, 8, 9, and A contain time of day and date
information (see Figure 2). Time of Day information is
stored in BCD. Registers 3, 5, and 7 contain the Time of
Day Alarm information. Time of Day Alarm information
is stored in BCD. Register B is the Command Register
and information in this register is binary. Registers C
and D are the Watchdog Alarm registers and informa-
tion which is stored in these two registers is in BCD.
Registers E through 3F are user bytes and can be used
to contain data at the user’s discretion.
相關(guān)PDF資料
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DS1286I 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
DS1286I+ 功能描述:實時時鐘 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
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