
DS1286
022798 5/12
TIME OF DAY REGISTERS
Registers 0, 1, 2, 4, 6, 8, 9, and A contain Time of Day
data in BCD. Ten bits within these eight registers are not
used and will always read zero regardless of how they
are written. Bits 6 and 7 in the Months Register (9) are
binary bits. When set to logic zero, EOSC (bit 7) enables
the Real Time Clock oscillator. This bit is set to logic one
as shipped from Dallas Semiconductor to prevent lithium
energy consumption during storage and shipment. This
bit will normally be turned on by the user during device
initialization. However, the oscillator can be turned on
and off as necessary by setting this bit to the appropriate
level. Bit 6 of this same byte controls the Square Wave
Output (Pin 23). When set to logic zero, the Square Wave
Output pin will output a 1024 Hz Square Wave Signal.
When set to logic one the Square Wave Output pin is in a
high impedance state. Bit 6 of the Hours Register is de-
fined as the 12– or 24– hour Select Bit. When set to logic
one, the 12–hour format is selected. In the 12–hour for-
mat, bit 5 is the AM/PM bit with logic one being PM. In the
24–hour mode, bit 5 is the second 10–hour bit (20–23
hours). The Time of Day registers are updated every .01
seconds from the real time clock, except when the TE bit
(bit 7 of Register B) is set low or the clock oscillator is not
running. The preferred method of synchronizing data ac-
cess to and from the Watchdog Timekeeper is to access
the Command Register by doing a write cycle to address
location 0B and setting the TE bit (Transfer Enable ) to a
logic zero. This will freeze the External Time of Day regis-
ters at the present recorded time, allowing access to oc-
cur without danger of simultaneous update. When the
watch registers have been read or written, a second write
cycle to location 0B, setting the TE bit to a logic one, will
put the Time of Day registers back to being updated every
0.01 second. No time is lost in the real time clock be-
cause the internal copy of the Time of Day register buffers
is continually incremented while the external memory
registers are frozen.
An alternate method of reading and writing the Time of
Day registers is to ignore synchronization. However,
any single read may give erroneous data as the real
time clock may be in the process of updating the exter-
nal memory registers as data is being read. The internal
copies of seconds through years are incremented and
Time of Day Alarm is checked during the period that
hundreds of seconds read 99 and are transferred to the
external register when hundredths of seconds roll from
99 to 00. A way of making sure data is valid is to do mul-
tiple reads and compare. Writing the registers can also
produce erroneous results for the same reasons. A way
of making sure that the write cycle has caused proper
update is to do read verifies and re–execute the write
cycle if data is not correct. While the possibility of erro-
neous results from reads and write cycles has been
stated, it is worth noting that the probability of an incor-
rect result is kept to a minimum due to the redundant
structure of the Watchdog Timekeeper.
TIME OF DAY ALARM REGISTERS
Registers 3, 5, and 7 contain the Time of Day Alarm regis-
ters. Bits 3, 4, 5, and 6 of Register 7 will always read zero
regardless of how they are written. Bit 7 of Registers 3, 5,
and 7 are mask bits (Figure 3). When all of the mask bits
are logic zero, a Time of Day Alarm will only occur when
Registers 2, 4, and 6 match the values stored in Regis-
ters 3, 5, and 7. An alarm will be generated every day
when bit 7 of Register 7 is set to a logic one. Similarly, an
alarm is generated every hour when bit 7 of Registers 7
and 5 is set to a logic 1. When bit 7 of Registers 7, 5, and
3 is set to a logic 1, an alarm will occur every minute when
Register 1 (seconds) rolls from 59 to 00.
Time of Day Alarm registers are written and read in the
same format as the Time of Day registers. The Time of
Day Alarm Flag and Interrupt is always cleared when
Alarm registers are read or written.
WATCHDOG ALARM REGISTERS
Registers C and D contain the time for the Watchdog
Alarm. The two registers contain a time count from
00.01 to 99.99 seconds in BCD. The value written into
the Watchdog Alarm Registers can be written or read in
any order. Any access to Registers C or D will cause the
Watchdog Alarm to reinitialize and clears the Watchdog
Flag bit and the Watchdog Interrupt Output. When a
new value is entered or the Watchdog Registers are
read, the Watchdog Timer will start counting down from
the entered value to zero. When zero is reached, the
Watchdog Interrupt Output will go to the active state.
The Watchdog Timer countdown is interrupted and rein-
itialized back to the entered value every time either of
the registers is accessed. In this manner, controlled pe-
riodic accesses to the Watchdog Timer can prevent the
Watchdog Alarm from ever going to an active level. If
access does not occur, countdown alarm will be repeti-
tive. The Watchdog Alarm registers always read the en-
tered value. The actual countdown register is internal
and is not readable. Writing Registers C and D to zero
will disable the Watchdog Alarm feature.