參數(shù)資料
型號: DS1258Y-70
廠商: DALLAS SEMICONDUCTOR
元件分類: Static RAM
英文描述: 128K X 16 NON-VOLATILE SRAM MODULE, 70 ns, DIP40
封裝: 0.740 INCH, EXTENDED MODULE, DIP-40
文件頁數(shù): 6/8頁
文件大?。?/td> 156K
代理商: DS1258Y-70
DS1258Y/AB
6 of 8
POWER-DOWN/POWER-UP CONDITION
POWER-DOWN/POWER-UP TIMING
(tA: 0
°C to 70°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CEU
, CEL at VIH before Power-Down
tPD
0
s
11
VCC slew from VTP to 0V
tF
300
s
VCC slew from 0V to VTP
tR
300
s
CEU
, CEL at VIH after Power-Up
tREC
2
125
ms
(tA=25
°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Expected Data Retention Time
tDR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
WE
is high for a Read Cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of CEU or CEL and WE . tWP is measured from the latter of CEU ,
CEL
or WE going low to the earlier of CEU , CEL or WE going high.
4. tDS is measured from the earlier of CEU or CEL or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CEU or CEL low transition occurs simultaneously with or later than the WE low transition in
the output buffers remain in a high impedance state during this period.
7. If the CEU or CEL high transition occurs prior to or simultaneously with the WE high transition, the
output buffers remain in high impedance state during this period.
相關(guān)PDF資料
PDF描述
DS1258Y-100 128K X 16 NON-VOLATILE SRAM MODULE, 100 ns, DIP40
DS1265AB-100 1M X 8 NON-VOLATILE SRAM MODULE, 100 ns, DMA36
DS1265Y-70 1M X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA36
DS1265AB 1M X 8 NON-VOLATILE SRAM MODULE, 70 ns, PDIP36
DS1265Y 1M X 8 NON-VOLATILE SRAM MODULE, 70 ns, PDIP36
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