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參數(shù)資料
| 型號(hào)： | DS1245Y |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | DRAM |
| 英文描述： | 1024K Nonvolatile SRAM(1024K 非易失性靜態(tài)RAM) |
| 中文描述： | 128K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA32 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 119K |
| 代理商： | DS1245Y |
DS1245Y/AB
042398 2/12
DESCRIPTION
The DS1245 1024K Nonvolatile SRAMs are1,048,576–
bit, fully static, nonvolatile SRAMs organized as
131,072 words by 8 bits. Each complete NV SRAM has
a self–contained lithium energy source and control cir-
cuitry which constantly monitors V
CC
for an out–of–tol-
erance condition. When such a condition occurs, the
lithium energy source is automatically switched on and
write protection is unconditionally enabled to prevent
data corruption. DIP–package DS1245 devices can be
used in place of existing 128K x 8 static RAMs directly
conforming to the popular bytewide 32–pin DIP stan-
dard. DS1245 devices in the PowerCap Module pack-
age are directly surface mountable and are normally
paired with a DS9034PC PowerCap to form a complete
Nonvolatile SRAM module. There is no limit on the num-
ber of write cycles that can be executed and no addition-
al support circuitry is required for microprocessor inter-
facing.
READ MODE
The DS1245 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip En-
able) and OE (Output Enable) are active (low). The
unique address specified by the 17 address inputs (A
0
–
A
16
) defines which of the 131,072 bytes of data is to be
accessed. Valid data will be available to the eight data
output drivers within t
ACC
(Access Time) after the last
address input signal is stable, providing that CE and OE
(Output Enable) access times are also satisfied. If OE
and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or
OE) and the limiting parameter is either t
CO
for CE or t
OE
for OE rather than address access.
WRITE MODE
The DS1245 devices execute a write cycle whenever
the WE and CE signals are active (low) after address in-
puts are stable. The later occurring falling edge of CE or
WE will determine the start of the write cycle. The write
cycle is terminated by the earlier rising edge of CE or
WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (t
WR
) before another cycle can
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in t
ODW
from its
falling edge.
DATA RETENTION MODE
The DS1245AB provides full functional capability for
V
CC
greater than 4.75 volts and write protects by
4.5 volts. The DS1245Y provides full functional capabil-
ity for V
CC
greater than 4.5 volts and write protects by
4.25 volts. Data is maintained in the absence of V
CC
without any additional support circuitry. The nonvolatile
static RAMs constantly monitor V
CC
. Should the supply
voltage decay, the NV SRAMs automatically write pro-
tect themselves, all inputs become “don’t care,” and all
outputs become high impedance. As V
CC
falls below
approximately 3.0 volts, a power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power–up, when V
CC
rises above approximately
3.0 volts, the power switching circuit connects external
V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds
4.75 volts for the DS1245AB and 4.5 volts for the
DS1245Y.
FRESHNESS SEAL
Each DS1245 device is shipped from Dallas Semicon-
ductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first
applied at a level greater than 4.25 volts, the lithium en-
ergy source is enabled for battery back–up operation.
PACKAGES
The DS1245 devices are available in two packages:
32–pin DIP and 34–pin PowerCap Module (PCM). The
32–pin DIP integrates a lithium battery, an SRAM
memory and a nonvolatile control function into a single
package with a JEDEC–standard 600 mil DIP pinout.
The 34–pin PowerCap Module integrates SRAM
memory and nonvolatile control along with contacts for
connection to the lithium battery in the DS9034PC Pow-
erCap. The PowerCap Module package design allows
a DS1245 PCM device to be surface mounted without
subjecting its lithium backup battery to destructive high–
temperature reflow soldering. After a DS1245 PCM is
reflow soldered, a DS9034PC PowerCap is snapped on
top of the PCM to form a complete Nonvolatile SRAM
module. The DS9034PC is keyed to prevent improper
attachment. DS1245 PowerCap Modules and
DS9034PC PowerCaps are ordered separately and
shipped in separate containers. See the DS9034PC
data sheet for further information.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS1245W | 3.3V 1024K Nonvolatile SRAM(3.3V 1024K 非易失性靜態(tài)RAM) |
| DS1248Y | Using the Dallas Phantom Real Time Clocks(帶幻象實(shí)時(shí)時(shí)鐘的NVSRAM) |
| DS1249AB | 2048K Nonvolatile SRAM(2048K 非易失性靜態(tài)RAM) |
| DS1249Y | 2048K Nonvolatile SRAM(2048K 非易失性靜態(tài)RAM) |
| DS1267 | Dual Digital Potentiometer Chip(雙路數(shù)字電位器芯片) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1245Y/AB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1024K Nonvolatile SRAM |
| DS1245Y_10 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:1024k Nonvolatile SRAM |
| DS1245Y-070 | 制造商:Maxim Integrated Products 功能描述: |
| DS1245Y-100 | 功能描述:NVRAM 1024K SRAM Nonvolatile RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS1245Y-100+ | 功能描述:NVRAM 1024K SRAM Nonvolatile RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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