參數(shù)資料
型號(hào)： DRV102T
英文描述： PWM SOLENOID/VALVE DRIVER
中文描述： 脈寬調(diào)制電磁/閥驅(qū)動(dòng)
文件頁(yè)數(shù)： 10/19頁(yè)
文件大?。?/td> 253K
代理商： DRV102T
10
DRV102
FIGURE 6. Simplified Circuit Model of the Duty Cycle
Adjust Pin.
FIGURE 5. Using a Voltage Source to Program Duty Cycle.
DRV102
D/A
Converter
(or analog
voltage)
1k
(1)
PWM
V
PWM
3
Gnd 4
6
5
V
S
Out
NOTE: (1) Required if voltage source can go below 0.1V.
200
μ
A
3
V
S
Comparator
Duty Cycle
Adjust
DRV102
19k
Resistor or
Voltage Source
(1)
NOTE: (1) Do not drive pin below 0.1V.
3.8V
0.7V
f = 24kHz
ADJUSTABLE DUTY CYCLE
The DRV102’s externally adjustable duty cycle provides an
accurate means of controlling power delivered to the load.
Duty cycle can be set from 10% to 90% with an external
resistor, analog voltage, or the output of a D/A converter.
Reduced duty cycle results in reduced power dissipation.
This keeps the DRV102 and load cooler, resulting in in-
creased reliability for both devices. PWM frequency is a
constant 24kHz.
Resistor-Controlled Duty Cycle
Duty cycle is independently programmed with a resistor
(R
PWM
) connected between the Duty Cycle Adjust pin and
ground. Increased resistor values correspond to decreased
duty cycles. Table II provides resistor values for typical duty
cycles. Resistor values for additional duty cycles can be
obtained from Figure 4. For reference purposes, the equation
for calculating R
PWM
is included in Figure 4.
FIGURE 4. R
PWM
versus Duty Cycle.
RESISTOR
(1)
R
PWM
(k
)
VOLTAGE
(2)
V
PWM
(V)
DUTY CYCLE
10
20
30
40
50
60
70
80
90
536
137
66.5
39.2
24.9
16.2
10.5
6.65
4.42
3.67
3.31
2.91
2.49
2.07
1.66
1.26
0.88
0.56
NOTES: (1) Resistor values listed are nearest 1% standard values. (2) Do not
drive pin below 0.1V. For additional values, see “Duty Cycle vs Voltage” typical
performance curve.
TABLE II. Duty Cycle Adjust. T
A
= +25
°
C, V
S
= +24V.
Voltage-Controlled Duty Cycle
Duty cycle can also be programmed with an analog voltage,
V
PWM
. With V
PWM
≈
0.5V, duty cycle is 100%. Increasing
this voltage results in decreased duty cycles. For 0% duty
cycle, V
PWM
is approximately 4V. Table II provides V
PWM
values for typical duty cycles. See the “Duty Cycle vs
Voltage” typical performance curve for additional duty cycle
values.
The Duty Cycle Adjust pin should not be driven below 0.1V.
If the voltage source used can go between 0.1V and ground,
a 1k
series resistor between the voltage source and the Duty
Cycle Adjust pin (Figure 5) is required to limit swing. If the
pin is driven below 0.1V, the output will be unpredictable.
The DRV102’s internal 24kHz oscillator sets the PWM
period. This frequency is not externally adjustable. Duty
Cycle Adjust (pin 3) is internally driven by a 200
μ
A current
source and connects to the input of a comparator and a 19k
resistor as shown in Figure 6. The DRV102’s PWM control
design is inherently monotonic. That is, a decreased voltage
(or resistor value) always produces an increased duty cycle.
10
20
40
60
100
80
Duty Cycle (%)
R
P
)
1000
100
10
1
R
PWM
= [ a + b (DC) + c (DC)
2
+ d (DC)
3
+ e (DC)
4
]
–1
where: a = –4.9686 x 10
–8
b = –5.9717 x 10
–8
c = 2.9889 x 10
–8
d = –5.4837 x 10
–10
e = 5.9361 x 10
–12
R
PWM
= [–4.9686 x 10
–8
+ (–5.9717 x 10
–8)
(50) + (2.9889 x 10
–8
) (50)
2
+ (–5.4837 x 10
–10
) (50)
3
+ (5.9361 x 10
–12
) (50)
4
]
–1
= 24.9k
DC = duty cycle in %
For 50% duty cycle:
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參數(shù)描述
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