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參數(shù)資料
| 型號(hào)： | DM93L01 |
| 文件頁(yè)數(shù)： | 155/158頁(yè) |
| 文件大?。?/td> | 2668K |
| 代理商： | DM93L01 |
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Switching Characteristics
V
CC
= +5.0V, T
A
= +25C
Symbol
Parameter
C
L
= 15 pF
Units
Min
Max
68
95
70
92
65
57
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay
B
n
or C
n
or Z
n
Propagation Delay
D
A
to Z
n
Propagation Delay
CP to Z
n
ns
ns
ns
Functional Description
The 93L38 8-bit multiple port register can be considered a
1-bit slice of eight high speed working registers. Data can be
written into any one and read from any two of the eight loca-
tions simultaneously. Master/slave operation eliminates all
race problems associated with simultaneous read/write ac-
tivity from the same location. When the clock input (CP) is
LOW data applied to the data input line (D
) enters the se-
lected master. This selection is accomplished by coding the
three write input select lines (A0–A2) appropriately. Data is
stored synchronously with the rising edge of the clock pulse.
The information for each of the two slaved (output) latches is
selected by two sets of read address inputs (B0–B2 and
C0–C2). The information enters the slave while the clock is
HIGH and is stored while the clock is LOW. If Slave Enable
is LOW (SLE), the slave latches are continuously enabled.
The signals are available on the output pins (Z
B
and Z
C
). The
input bit selection and the two output bit selections can be
accomplished independently or simultaneously. The data
flows into the device, is demultiplexed according to the state
of the write address lines and is clocked into the selected
latch. The eight latches function as masters and store the in-
put data. The two output latches are slaves and hold the data
during the read operation. The state of each slave is deter-
mined by the state of the master selected by its associated
set of read address inputs.
The method of parallel expansion is shown in Figure 1 One
93L38 is needed for each bit of the required word length. The
read and write input lines should be connected in common
on all of the devices. This register configuration provides two
words of n-bits each at one time, where n devices are con-
nected in parallel.
DS010202-4
FIGURE 1. Parallel Expansion
3
www.fairchildsemi.com
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PDF描述 |
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| DM93L08 | |
| DM93L09 | |
| DM93L10 | |
| DM93L12 | |
| DM93L16 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM93L08 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DM93L09 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DM93L10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DM93L12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| DM93L14 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Quad Latch |
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