參數(shù)資料
型號(hào): DM93L01
文件頁(yè)數(shù): 141/158頁(yè)
文件大?。?/td> 2668K
代理商: DM93L01
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Switching Characteristics
V
CC
= +5.0V, T
A
= +25C (See Section 1 for test waveforms and output load)
Symbol
Parameter
C
L
= 15 pF
Units
Min
5.0
Max
f
max
t
PLH
t
PHL
t
PHL
Maximum Shift Right Frequency
Propagation Delay
CP to Q
7
or Q
7
Propagation Delay MR to Q
7
MHz
ns
45
80
110
ns
Functional Description
The two 8-bit shift registers have a common clock input (pin
9) and separate clock inputs (pins 10 and 7). The clocking of
each register is controlled by the OR function of the separate
and the common clock input. Each register is composed of
eight clocked RS master/slave flip-flops and a number of
gates. The clock OR gate drives the eight clock inputs of the
flip-flops in parallel. When the two clock inputs (the separate
and the common) to the OR gate are LOW, the slave latches
are steady, but data can enter the master latches via the R
and S input. During the first LOW-to-HIGH transition of ei-
ther, or both simultaneously, of the two clock inputs, the data
inputs (R and S) are inhibited so that a later change in input
data will not affect the master; then the now trapped informa-
tion in the master is transferred to the slave. When the trans-
fer is complete, both the master and the slave are steady as
long as either or both clock inputs remain HIGH. During the
HIGH-to-LOW transition of the last remaining HIGH clock in-
put, the transfer path from master to slave is inhibited first,
leaving the slave steady in its present state. The data inputs
(R and S) are enabled so that new data can enter the mas-
ter. Either of the clock inputs can be used as clock inhibit in-
puts by applying a logic HIGH signal. Each 8-bit shift register
Logic Diagram
has a 2-input multiplexer in front of the serial data input. The
two data inputs D0 and D1 are controlled by the data select
input (S) following the Boolean expression:
Serial data in: S
D
= SD0 + SD1
An asynchronous master reset is provided which, when acti-
vated by a LOW logic level, will clear all 16 stages indepen-
dently of any other input signal.
Shift Select Table
Inputs
D0
L
H
X
X
Output
Q7 (t
n+8
)
L
H
L
H
S
L
L
H
H
D1
X
X
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
n+8 = Indicates state after eight clock pulse
DS010200-3
3
www.fairchildsemi.com
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