
DM9331
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
8
Preliminary
Version: DM9331-DS-P02
September 21, 2001
Mode, 1 pin
Pin No.
10
Pin Name
PWRDWN
I/O
I
Description
Power down control
Asserted high to force DM9331 into power down mode. When in power
down mode, most of the DM9331 circuit block’s power is turned off, only
the MII management interface (MDC, MDIO) logic is available. To leave
power down mode, DM9331 need the hardware or software reset with
the PWRDWN pin low.
Bias and clock, 3 pins
Pin No.
47
48
43
Pin Name
BGRESG
BGRES
OSCIN
I/O
P
I/O Bandgap Voltage Reference Resistor 6.8K ohm
I
3.3V 50MHz clock input.must be using 3.3v output oscillators.
Description
Bandgap Ground
Power, 15 pins
Pin No.
1,2,9
5,6,46
16,23,30,31,
39,41
15,33,44
Pin Name
AVDD
AGND
DVDD
I/O
P
P
P
Description
Analog Power
Analog Ground
Digital Power
DGND
P
Digital Ground
Table A
OP2
OP1
OP0
Function
0
0
0
Auto negotiation enables 100TX Full/Half
capabilities
Manually select 100FX HDX
0
0
1
0
1
0
Manually select 100FX FDX
1
0
1
Manually select 100TX HDX