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參數(shù)資料
| 型號： | DM9008F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA/Plug & Play Super Ethernet Contoller |
| 中文描述： | 的ISA /插頭 |
| 文件頁數(shù)： | 37/68頁 |
| 文件大?。?/td> | 403K |
| 代理商： | DM9008F |
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DM9008
ISA/Plug & Play Super Ethernet Contoller
Final
Version :DM9008-DS-F02
June 14, 2000
37
ENC Module
Transmit Parallel/Serial
At the beginning of each transmission, the preamble and
synch generators append 62 bits of 1, 0 preamble and 1, 1
synch pattern. The parallel data from the FIFO are then
serialized for transmission. The serial data are also shifted into
the CRC generator. After the last data byte has been
serialized, the 32-bit FCS field is shifted directly out of the CRC
generator.
Receive Serial/Parallel
When the RX
±
input signal from ENA becomes active, the
incoming serial data are shifted into the shift register. The
receiver will detect the SFD to establish where byte boundaries
are located. The serial data are also routed to the CRC
checker. After every eight receive clocks, the byte-wide data
are transferred to the FIFO, and the receive byte count is
incremented.
Address Recognition Logic
There are three types of address recognition logic. The first 6-
byte destination address field of the received packet is
compared to the physical address registers. The packet will be
rejected if the field and registers do not match. Multicast
destination addresses are filtered using a hashing technique.
The packet is accepted only if the multicast address indexes a
bit that has been set in the filter bit array of the multicast
address registers. Each destination address is also checked
for all 1's, which is the reserved broadcast address.
16-Byte FIFO
Through local DMA operation, parallel data can be transferred
to or from the 16-byte FIFO during transmission and reception.
The DMA begins a bus access and writes/reads data to/from
the FIFO before a FIFO underrun/overrun occurs. Because the
DM9008 must buffer the address field of an incoming packet to
make a decision, the first local DMA transfer does not occur
until 8 bytes have accumulated in the FIFO. The FIFO logic
will flag a FIFO overrun when the 13th byte is written to the
FIFO.
CRC Generator/Checker
During transmission, the CRC encodes all fields after the
synch bits to generate a local CRC field. The CRC is shifted
out MSB first following the transmit byte. During reception, the
CRC logic generates a CRC field from the incoming packet.
This local CRC is serially compared to the incoming CRC to
check whether the incoming packet is correct.
DMA Registers and Control Logic
Two 16-bit DMA channels are provided. The local DMA stores
received packets in a receive buffer ring during reception and
transfers a packet from local buffer memory to the FIFO during
transmission. The remote DMA is used to transfer data
between the local buffer memory and the host system. Both
are internally arbitrated, with the local DMA channel having
highest priority. External arbitration is performed with a
standard bus request, bus acknowledge handshake protocol.
Protocol Control Logic
The protocol control logic implements the IEEE 802.3 protocol,
including collision recovery with random backoff. The protocol
control logic also formats packets during transmission, as well
as strips preamble and synch during reception.
Direct Memory Access Control (DMA)
DM9008 provides DMA capabilities to simplify buffer data
transfer. The local DMA channel transfers data between the
FIFO and buffer. On reception, packets are transferred from
the FIFO to the receive buffer ring in bursts. During
transmission, the packets are transferred in the opposite
direction from the buffer to the FIFO.
A remote DMA channel is provided to accomplish transfers
between buffer memory and system memory. The ENC's local
DMA channel performs burst transfers between the buffer
memory and DM9008's FIFO. The remote DMA transfers data
between the buffer memory and the host memory via
bidirectional latches. The DM9008 allows local and remote
DMA
operations
to
be
interleaved.
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