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參數(shù)資料
| 型號(hào)： | DM9008F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA/Plug & Play Super Ethernet Contoller |
| 中文描述： | 的ISA /插頭 |
| 文件頁數(shù)： | 34/68頁 |
| 文件大小： | 403K |
| 代理商： | DM9008F |
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DM9008
ISA/Plug & Play Super Ethernet Contoller
the card resource data is accessed. The Vendor ID and Unique
Serial Number are valid; however, the checksum byte, when
read in this way, is not valid. For a card that enters the Config
state from the isolation state, the first read of the resource Data
register will return resource data.
34
Final
Version :DM9008-DS-F02
June 14, 2000
Reading Resource Data
Each PnP card supports a resource data structure stored in a
non-volatile device (e.g. 9346) that describes the resources
requested by the card. The Plug and Play resource
management software will arbitrate resources and set up the
logical device configuration registers according to the resource
data.
Card resource data may only be read from cards in the Config
state. A card may get to the Config state by one of two different
methods:.1) A card enters the Config state in response to the
card "winning" the serial isolation protocol and having a CSN
assigned, or 2) the card receives a Wake[CSN] command that
matches the card's CSN.
As described above, all Plug and Play cards function as if their
serial identifier and their resource data both come from the
same serial device. As also stated above, the pointer to the
serial device is reset in response to any Wake[CSN]
command. This implies that if a card enters the Config state
directly from sleep state in response to a Wake[CSN]
command, the 9-byte serial identifier must first be read before
Card resource data is read by first polling the Status register
and waiting for bit[0] to be set. When this bit is set, one byte of
resource data is ready to be read from the Resource data
register. After the Resource Data register is read, the Status
register must be polled before reading the next byte of
resource data. This process is repeated until all resource data
is read.
The above operation implies that the hardware is responsible
for accumulating 8 bits of data in the Resource Data register.
When this operation is complete, the status bit[0] is set. When
a read is performed on the Resource Data register, status bit[0]
is cleared, eight more bits are shifted into the Resource Data
register, and
the status bit[0] is set again.
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