- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376802 > DM9008 (Electronic Theatre Controls, Inc.) ISA/Plug & Play Super Ethernet Contoller PDF資料下載
參數(shù)資料
| 型號： | DM9008 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA/Plug & Play Super Ethernet Contoller |
| 中文描述： | 的ISA /插頭 |
| 文件頁數(shù)： | 43/68頁 |
| 文件大?。?/td> | 403K |
| 代理商： | DM9008 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
DM9008
ISA/Plug & Play Super Ethernet Contoller
D8
D7
Final
Version :DM9008-DS-F02
June 14, 2000
43
Prior to transmission, TPSR and TBCR0, TBCR1 must be
initialized. To initiate transmission of the packet, the TXP bit in
the Command Register is set. The Transmit Status Register
(TSR) is cleared and DM9008 begins to transmit data from
memory (unless the ENC is currently receiving). If the
interframe gap has timed out, ENC will begin transmission.
Collision Recovery
During transmission, Buffer Management logic monitors the
transmit circuitry to determine whether a collision has
occurred. If a collision is detected, the Buffer Management
logic will reset the FIFO and restore the Transmit DMA pointers
for retransmission of the packet. The COL bit will be set in TSR
and NCR (Number of Collisions Register) will be incremented.
If 15 successive retransmissions each result in a collision, the
transmission will be aborted and the ABT bit in TSR will be set.
Note: NCR reads as all zeroes if excessive collisions are
encountered.
Transmit Packet Assembly Format
The following diagrams describe the format for assembling
packets prior to transmission for different byte ordering
schemes. The various formats are selected in the DCR.
D15
D8
D7
D0
DA1
DA0
DA3
DA2
DA5
DA4
SA1
SA0
SA3
SA2
SA5
SA4
T/L1
T/L0
DATA1
DATA0
BOS=0, WTS=1 in DCR
This format is used with Series 32000 808X-type processors.
D15
D0
DA0
DA1
DA2
DA3
DA4
DA5
SA0
SA1
SA2
SA3
SA4
SA5
T/L0
T/L1
DATA0
DATA1
BOS =1, WTS = 1 in DCR
This format is used with 68000-type processors.
D7
D0
DA0
DA1
DA2
DA3
DA4
DA5
SA0
SA1
BOS = 0, WTS = 0 in DCR
This format is used with general 8-bit CPUs.
Loopback Diagnostics
Three forms of local loopback are provided on the DM9008.
The user has the ability to loop back through the deserializer
on the ENC, through the ENA, and to the co-ax to check the
link via the transceiver circuitry. Because of the half duplex
architecture of DM9008, loopback testing is a special mode of
operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9008F | ISA/Plug & Play Super Ethernet Contoller |
| DM9081 | 10BASE-T Hub Controller |
| DM9081F | 10BASE-T Hub Controller |
| DM9095 | Twisted-Pair Medium Attachment Unit |
| DM9095L | Twisted-Pair Medium Attachment Unit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9008AEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
| DM9008AEP_06 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
| DM9008AEP_08 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
| DM9008C | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller With General Processor Interface |
| DM9008CEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller With General Processor Interface |
發(fā)布緊急采購，3分鐘左右您將得到回復。