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參數資料
| 型號： | DM9008 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA/Plug & Play Super Ethernet Contoller |
| 中文描述： | 的ISA /插頭 |
| 文件頁數： | 23/68頁 |
| 文件大?。?/td> | 403K |
| 代理商： | DM9008 |
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DM9008
ISA/Plug & Play Super Ethernet Contoller
Physical Address Register (PAR0-PAR5)
Final
Version :DM9008-DS-F02
June 14, 2000
23
Network Tally Counter Registers (CNTR)
Three 8-bit counters are provided for monitoring the number of
CRC errors, Frame Alignment Errors and Missed Packets. The
maximum count reached by any counter is 192 (C0H). These
registers will be cleared when read by the CPU. The count is
recorded in binary in CT0-CT7 of each Tally Register.
CNTR0: Monitors the number of Frame Alignment errors
7
6
5
4
3
2
1
0
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
CNTR1: Monitors the number of CRC errors
7
6
5
4
3
2
1
0
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
CNTR2: Monitors the number of Missed Packets
7
6
5
4
3
2
1
0
CT7
CT6
CT5
CT4
CT3
CT2
CT1
CT0
Number of Collisions Register (NCR)
This register contains the number of collisions a node
experiences when attempting to transmit a packet. If no
collisions are experienced during a transmission attempt, the
COL bit of the TSR will not be set and the contents of NCR will
be zero. If there are excessive collisions, the ABT bit in the
TSR will be set and the contents of NCR will be zero. NCR is
cleared after TXP in CR is set.
7
6
5
4
3
2
1
0
NCR
0
0
0
0
NC3
NC2
NC1
NC0
FIFO Register (FIFO)
This is an 8-bit register that allows the CPU to examine the
contents of the FIFO after loopback. The FIFO will contain the
last 8 data bytes transmitted in the loopback packet.
Sequential reads from the FIFO will advance a pointer in the
FIFO and allow reading of all 8 bytes. Note that the FIFO
should only be read when DM9008 has been programmed in
loopback mode.
7
6
5
4
3
2
1
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
The Physical Address Registers are used to compare the
destination addresses of incoming packets to be rejected or
accepted. Comparisons are performed on a byte-wide basis.
The bit assignment shown below relates the sequence in
PAR0-PAR5 to the bit sequence of the received packet.
. .
Sy
n
Sy
n
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
. .
Destination Address
Sou
D7
D6
D5
D4
D3
D2
D1
D0
PAR0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
PAR1
DA15
DA14
DA13
DA12
DA11
DA10
DA9
DA8
PAR2
DA23
DA22
DA21
DA20
DA19
DA18
DA17
DA16
PAR3
DA31
DA30
DA29
DA28
DA27
DA26
DA25
DA24
PAR4
DA39
DA38
DA37
DA36
DA35
DA34
DA33
DA32
PAR5
DA47
DA46
DA45
DA44
DA43
DA42
DA41
DA40
Multicast Address Registers (MAR0-MAR7)
The Multicast Address Registers provide filtering of multicast
addresses hashed by the CRC logic. All destination addresses
are fed through the CRC logic. When the last bit of the
destination address enters the CRC, the 6 most significant bits
of the CRC generator are latched. These 6 bits are then
decoded by a 1 of 64 decode to index a unique filter bit (FB0-
63) in the multicast address registers. If the filter bit selected is
set, the multicast packet is accepted. The system designer
uses a program to determine which filter bits to set in the
multicast registers. If an address is found to hash to the value
50(32H), then FB50 in MAR6 should be initialized to 1. All
multicast filter bits that correspond to the multicast address
accepted by the node are then set to one. To accept all
multicast packets, all of the registers are set to all ones.
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| DM9008AEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
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| DM9008C | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller With General Processor Interface |
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