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參數(shù)資料
| 型號： | DM7474 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs(雙正邊緣觸發(fā)的D觸發(fā)器（帶預(yù)置、清除端和互補輸出）) |
| 中文描述： | 雙上升沿觸發(fā)D型觸發(fā)器與預(yù)設(shè)，明確和互補輸出（雙正邊緣觸發(fā)的?觸發(fā)器（帶預(yù)置，清除端和互補輸出）） |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 51K |
| 代理商： | DM7474 |
2000 Fairchild Semiconductor Corporation
DS006526
www.fairchildsemi.com
September 1986
Revised February 2000
D
DM7474
Dual Positive-Edge-Triggered D-Type Flip-Flops with
Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D-type flip-flops with complementary outputs. The
information on the D input is accepted by the flip-flops on
the positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as the data
setup and hold times are not violated. A LOW logic level on
the preset or clear inputs will set or reset the outputs
regardless of the logic levels of the other inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
L
=
LOW Logic Level
↑
=
Positive-going transition of the clock.
Q
0
=
The output logic level of Q before the indicated input conditions were
established.
Note 1:
This configuration is nonstable; that is, it will not persist when either
the preset and/or clear inputs return to their inactive (HIGH) level.
Order Number
DM7474M
DM7474N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
PR
L
H
L
CLR
H
L
L
CLK
X
X
X
D
X
X
X
Q
H
L
H
Q
L
H
H
(Note 1)
H
L
Q
0
(Note 1)
L
H
Q
0
H
H
H
H
H
H
↑
↑
L
H
L
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM7474M | Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs |
| DM7474N | Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs |
| DM7476 | Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs(雙主從J-K觸發(fā)器(帶預(yù)置、清除端和互補輸出)) |
| DM7476N | Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs |
| DM7486 | Quad 2-Input Exclusive-OR Gate(四2輸入異或門) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM7474J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| DM7474J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| DM7474M | 功能描述:觸發(fā)器 Dl D-Type Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM7474MX | 功能描述:觸發(fā)器 RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM7474N | 功能描述:觸發(fā)器 Dl JK M/S Flip Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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