- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376778 > DM7476 (Fairchild Semiconductor Corporation) Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs(雙主從J-K觸發(fā)器(帶預(yù)置、清除端和互補(bǔ)輸出)) PDF資料下載
參數(shù)資料
| 型號： | DM7476 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs(雙主從J-K觸發(fā)器(帶預(yù)置、清除端和互補(bǔ)輸出)) |
| 中文描述： | 雙主從JK觸發(fā)器明確，預(yù)設(shè)和互補(bǔ)輸出（雙主從JK觸發(fā)器（帶預(yù)置，清除端和互補(bǔ)輸出）） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 41K |
| 代理商： | DM7476 |
2000 Fairchild Semiconductor Corporation
DS006528
www.fairchildsemi.com
September 1986
Revised February 2000
D
DM7476
Dual Master-Slave J-K Flip-Flops with
Clear, Preset, and Complementary Outputs
General Description
This device contains two independent positive pulse trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop after a complete clock
pulse. While the clock is LOW the slave is isolated from the
master. On the positive transition of the clock, the data
from the J and K inputs is transferred to the master. While
the clock is HIGH the J and K inputs are disabled. On the
negative transition of the clock, the data from the master is
transferred to the slave. The logic state of J and K inputs
must not be allowed to change while the clock is HIGH.
The data is transferred to the outputs on the falling edge of
the clock pulse. A LOW logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
Ordering Code:
Connection Diagram
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
=
Positive pulse data. The J and K inputs must be held constant while
the clock is HIGH. Data is transferred to the outputs on the falling
edge of the clock pulse.
Q
0
=
The output logic level before the indicated input conditions were
established.
Toggle
=
Each output changes to the complement of its previous level on
each complete active HIGH level clock pulse.
Note 1:
This configuration is nonstable; that is, it will not persist when the
preset and/or clear inputs return to their inactive (HIGH) level.
Order Number
DM7476N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
PR
L
H
L
CLR
H
L
L
CLK
X
X
X
J
X
X
X
K
X
X
X
Q
H
L
H
Q
L
H
H
(Note 1)
Q
0
H
L
(Note 1)
Q
0
L
H
H
H
H
H
H
H
H
H
L
H
L
H
L
L
H
H
Toggle
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM7476N | Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs |
| DM7486 | Quad 2-Input Exclusive-OR Gate(四2輸入異或門) |
| DM7486N | Quad 2-Input Exclusive-OR Gate |
| DM7490A | Decade and Binary Counters(十進(jìn)制和二進(jìn)制計(jì)數(shù)器) |
| DM7490AN | Decade and Binary Counters |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM7476_01 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs |
| DM7476J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| DM7476N | 功能描述:觸發(fā)器 Dual J-K Flip-Flop RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| DM7476N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
| DM7476N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。