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參數(shù)資料
| 型號(hào)： | DM7474N |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs |
| 中文描述： | TTL/H/L SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-14 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 51K |
| 代理商： | DM7474N |
2000 Fairchild Semiconductor Corporation
DS006526
www.fairchildsemi.com
September 1986
Revised February 2000
D
DM7474
Dual Positive-Edge-Triggered D-Type Flip-Flops with
Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D-type flip-flops with complementary outputs. The
information on the D input is accepted by the flip-flops on
the positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as the data
setup and hold times are not violated. A LOW logic level on
the preset or clear inputs will set or reset the outputs
regardless of the logic levels of the other inputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
L
=
LOW Logic Level
↑
=
Positive-going transition of the clock.
Q
0
=
The output logic level of Q before the indicated input conditions were
established.
Note 1:
This configuration is nonstable; that is, it will not persist when either
the preset and/or clear inputs return to their inactive (HIGH) level.
Order Number
DM7474M
DM7474N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Outputs
PR
L
H
L
CLR
H
L
L
CLK
X
X
X
D
X
X
X
Q
H
L
H
Q
L
H
H
(Note 1)
H
L
Q
0
(Note 1)
L
H
Q
0
H
H
H
H
H
H
↑
↑
L
H
L
X
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