參數(shù)資料
型號(hào)： DLPC200ZEWT
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA780
封裝： PLASTIC, FBGA-780
文件頁數(shù)： 27/42頁
文件大?。?/td> 937K
代理商： DLPC200ZEWT
www.ti.com
DLPS014B – APRIL 2010 – REVISED DECEMBER 2010
DDR2 SDR Memory Interface (continued)
going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are
registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM
are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a
programmed sequence.
Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the ACTIVATE command are used to select the bank and
row to be accessed. The address bits registered coincident with the READ or WRITE command are used to
select the bank and the starting column location for the burst access.
DDR2 SDR MEMORY INTERFACE TIMING REQUIREMENTS
PARAMETER
MIN
MAX
UNIT
tCYCLE
Cycle time reference
5.0
8.0
ns
tCH
CK high pulse width(1)
2.4
4.16
ns
tCL
CK low pulse width(1)
2.4
4.16
ns
tCMS
Command setup
200
ps
tCMH
Command hold
275
ps
tAS
Address setup
400
ps
tAH
Address hold
400
ps
tDS
Write data setup
1.5
ns
tDH
Write data hold
1.5
ns
tAC
Read data access time
-450
450
ps
tOH
Read data hold time
340
ps
tLZ
Read data low impedance time
-900
450
ps
tHZ
Read data high impedance time
450
ps
(1)
Output setup/ hold numbers already account for controller clock jitter. Only routing skew and memory setup/ hold need be considered in
system timing analysis.
Copyright 2010, Texas Instruments Incorporated
33
Product Folder Link(s): DLPC200
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