參數(shù)資料
型號(hào)： DLPC200ZEWT
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA780
封裝： PLASTIC, FBGA-780
文件頁(yè)數(shù)： 16/42頁(yè)
文件大?。?/td> 937K
代理商： DLPC200ZEWT
0-505 bytes
1 byte
Header
Data
Checksum
CMD4
1 byte
Len_LSB
1 byte
Len_MSB
1 byte
CMD3
1 byte
CMD2
1 byte
CMD1
1 byte
www.ti.com
DLPS014B – APRIL 2010 – REVISED DECEMBER 2010
USB Interface
The USB Interface consists of a single chip integrated USB 2.0 tranceiver, smart SIE, and enhance 8051
microprocessor running at 48 MHz (nominal) that support USB 2.0.
Bus Protocol
USB is a polled bus. The host controller (typically at PC) initiates all data transfers. Each transaction begins
when the PC sends a packet. Communications will always be through the bulk transfer mode and 512 bytes of
data are always written/read at a time. The packet consists of the following:
Header (6 bytes)
Data (505 bytes)
Checksum (1 byte)
The USB device that is addressed selects itself by decoding the appropriate address fields. The direction of data
transfer, either read or write, is specified in the packet header. The source of the transaction then sends a data
packet or indicates it has no data to transfer. At the end of either a single packet transfer or a multi-packet
transfer, the destination responds with a handshake packet indicating whether the transfer was successful.
Packet header consists of a
CMD1 - indicates if packet is write/write response or read/read response
CMD2 - groups major functions together
CMD3 - provides more information about packet grouping defined in CMD2
CMD4 - used to indicate location of data in a multi-packet transfer
Len_MSB:Len_LSB - valid number of bytes of data transfered in packet data
Figure 5. USB Data Packet
As discussed above, the header describes whether the data transaction will be a read or write and designates
the data endpoint. The data portion of the packet carries the payload and is followed by an handshaking
mechanism, checksum, that reports if the data was received successfully, or if the endpoint is stalled or not
available to accept data.
USB READ INTERFACE TIMING REQUIREMENTS
PARAMETER
MIN
Typ
MAX
UNIT
tCL
1/CLKOUT Frequency
20.8
ns
tAV
Delay from clock to valid address
10.7
ns
tSTBL
Clock to USB_RDY0 LOW
11
ns
tSTBH
Clock to USB_RDY0 HIGH
11
ns
tSCSL
Clock to USB_PA02 LOW
13
ns
tDSU
Data setup to clock
9.6
ns
tDH
Data hold time
0
ns
tACC1
valid USB_PA04 to valid USB_FDC
43
ns
Copyright 2010, Texas Instruments Incorporated
23
Product Folder Link(s): DLPC200
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