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參數(shù)資料
| 型號： | DLPC200ZEWT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA780 |
| 封裝： | PLASTIC, FBGA-780 |
| 文件頁數(shù)： | 19/42頁 |
| 文件大小： | 937K |
| 代理商： | DLPC200ZEWT |
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SPI_CLK
SPI_DATA
t
p_su
t
p_h
t
p_wh
t
p_wl
t
p_clkper
DLPS014B – APRIL 2010 – REVISED DECEMBER 2010
www.ti.com
SPI Slave Interface (continued)
BUSY — hold off signal to indicate that the slave is processing commands and cannot accept new input
(output from slave)
The master pulls the slave select low. During each SPI clock cycle, a full duplex data transmission occurs:
The master sends a bit on the MOSI line; the slave reads it from that same line
The slave sends a bit on the MISO line; the master reads it from that same line
Transmissions involve two shift registers, one in the master and one in the slave; they are connected in a ring.
Data is shifted out with the most significant bit first, while shifting a new least significant bit into the same
register.
After that register has been shifted out, the master and slave have exchanged register values. If there is more
data to exchange, the shift registers are loaded with new data and the process repeats. Transmissions may
involve any number of clock cycles.
When there is no more data to be transmitted, the master stops toggling its clock. Transmissions consist of
packet commands/responses similar to the protocol defined for the USB interface. The SPI slave supports
variable length command and response packets and a master can initiate multiple such transmissions as
needed.
SPI INTERFACE TIMING REQUIREMENTS
PARAMETER
MIN
MAX
UNIT
fclock
Clock frequency, SPI_CLK
5
MHz
tp_clkper
Clock period, SPI_CLK
200
ns
tp_wh
Pulse width low, SPI_CLK
10
ns
tp_wl
Pulse width high, SPI_CLK
10
ns
tp_su
Setup Time – SPI_DIN valid before SPI_CLK rising edge
10
ns
tp_h
Hold Time – SPI_DIN valid after SPI_CLK rising edge
5
ns
Figure 8. SPI Slave Timing
Parallel Flash Memory Interface
The Controller Parallel Flash Memory interface supports a high-speed NOR device with a 16 bit data bus and up
to 1GB of memory.
To perform a synchronous burst read on array or non-array, an initial address is driven onto the address bus,
and CE is asserted. WE and RST must already have been deasserted. ADV is asserted, and then deasserted to
latch the address. Alternately, ADV can remain asserted throughout the burst access, in which case the address
is latched on the next valid CLK edge while ADV is asserted. Once OE is asserted, the the first word is driven
onto DQ[15:0] on the next valid CLK edge after initial access latency delay. Subsequent data is output on valid
CLK edges following a minimum delay Tchqv.
26
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): DLPC200
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