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8
DEM-DAI
A/D CONVERTERS
There are three configurations for testing PCM ADC prod-
ucts. They are shown in Figures 12, 13, and 14.
This includes two Slave mode configurations and one Mas-
ter mode configuration.
Figure 12 shows the ADC Slave Configuration #1. This
setup uses the CS8412 receiver to recover the audio clocks
from a S/PDIF data stream. The clocks are supplied to both
the ADC and the CS8402A transmitter. Data from the ADC
is routed to the CS8402A transmitter and output as a S/PDIF
data stream on both an optical transmitter (U10) and a RCA
connector (J2).
FIGURE 12. ADC Slave Configuration #1.
Table VI shows the DEM-DAI board switch and jumper
configurations for ADC Slave Configuration #1.
SWITCH/JUMPER
CONFIGURATION
SW1, SW2, SW3
Setup to match the corresponding ADC data
format.
SW4, SW5, SW6
Setup to match the corresponding ADC data
format.
SW7
Set to Slave mode.
SW9
PRO = H; FC0 and FC1 = sample rate in use;
all others = L.
JP1
Set to NML.
JP2
Set to DIR.
JP3
Set to DIR.
JP4
Not used, but set to 256/512 f
S
.
JP5
Set to DIR1.
JP6
Set to NML.
TABLE VI. Switch and Jumper Settings for ADC Slave
Configuration #1.
Figure 13 shows the ADC Slave Configuration #2. The
crystal oscillator/divider circuit is used to generate the clocks
for the ADC and CS8402A transmitter. The CS8412 receiver
is not used in this configuration. Data from the ADC is
routed to the CS8402A and transmitted as an S/PDIF data
stream at both optical (U10) and RCA (J2) connectors.
Unlike ADC Slave Configuration #1, the user must choose
the system clock rate and configure the jumpers for system,
left/right, and bit clocks accordingly. As an example, if you
select the system clock to be 512 f
S
, then jumpers JP2
through JP5 must be set for 512 f
S
operation.
ADC Slave Configuration #2 does not support I
2
S format. It
only supports standard right or left justified data formats.
FIGURE 13. ADC Slave Configuration #2.
Table 7 shows the DEM-DAI board switch and jumper
configurations for ADC Slave Configuration #2
SWITCH/JUMPER
CONFIGURATION
SW1, SW2, SW3
Setup to match the SW4, SW5, and SW6
settings.
SW4, SW5, SW6
Setup to match the corresponding ADC data
format.
SW7
Set to Slave mode.
SW9
PRO = H; FC0 and FC1 = sample rate in use;
all others = L.
JP1
Set to XTAL.
JP2
Set to 256, 384, or 512.
JP3
Set to 256, 384, or 512.
JP4
Set to 256/512 f
S
or 384 f
S
.
Set to 384 f
, 512 f
S
, or DIR1 (for 256 f
S
XTAL operation).
JP5
JP6
Set to NML.
TABLE VII. Switch and Jumper Settings for ADC Slave
Configuration #2.
CS8412
Analog
Input
DEM-PCM
Evaluation
Board
CS8402A
LRCK, BCK
LRCK
BCK
SYSCLK
Data
XTAL OSC
and
Divider
Analog
Input
DEM-PCM
Evaluation
Board
CS8402A
LRCK, BCK
LRCK
BCK
SYSCLK
Data