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參數(shù)資料
| 型號： | DEM-DSP102 |
| 英文描述： | DEM-DSP102 - DISCONTINUED PRODUCT. No longer recommended for new design. |
| 中文描述： | 馬克- DSP102 -已停產(chǎn)產(chǎn)品。不再推薦用于新設(shè)計(jì)。 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 194K |
| 代理商： | DEM-DSP102 |
7
DEM-DAI
JP5
512
384
DIR1
DIR2
When using 512 f
S
clock from crystal oscillator/divider
When using 384 f
S
clock from crystal oscillator/divider
When using 256 f
clock from crystal oscillator/divider
or when using digital audio receiver as system clock source
When using transmitter in Transparent mode
JP3 is used to select the left/right clock (LRCK) source.
Figure 7 shows the header block with descriptions for each
of the four options. The left/right clock rate is equal to the
sampling frequency.
TYPICAL DEM-DAI TEST
CONFIGURATIONS
This section provides general information for configuring
the DEM-DAI board for testing Burr-Brown’s PCM audio
devices. Refer to the individual PCM product and demon-
stration board data sheets for more detailed information
regarding product operation and demo board configuration.
D/A CONVERTERS
The general test configuration for PCM DACs is shown in
Figure 11. This setup uses the CS8412 receiver to recover
the audio clocks and data from a S/PDIF data stream. The
system clock, left/right clock, bit clock, and data are then
routed from the receiver to the DEM-PCM demo board to
operate the PCM DAC. The left and right outputs of the
DAC are routed to the on-board post filters to remove out-
of-band noise and otherwise band limit the output signal.
The output of the filters is available at the J3 and J4 RCA
connectors.
FIGURE 11. DAC Configuration.
SWITCH/JUMPER
CONFIGURATION
SW1, SW2, SW3
Setup to match the corresponding DAC data
format.
SW4, SW5, SW6
Setup to match SW1, SW2, and SW3.
SW7
Set to Slave mode.
SW9
PRO = H; FC0 and FC1 = sample rate in use;
all others = L.
JP1
Set to NML.
JP2
Set to DIR.
JP3
Set to DIR.
JP4
Not used, but set to 256/512 f
S
.
JP5
Set to DIR1.
JP6
Not used, but set to NML.
Table V shows the DEM-DAI board switch and jumper
configurations for PCM DAC testing.
TABLE V. Switch and Jumper Settings for PCM DAC
Testing.
FIGURE 7. Word Clock Source Selection.
JP4 is used to select the system clock rate when using the
crystal oscillator as the system clock source. Figure 8 shows
the header block with descriptions for the two available
options. The 256/512 f
S
rate is determined by the frequency
of the crystal oscillator used.
FIGURE 8. System Clock Rate Selection When Using the
Crystal Oscillator/Divider.
JP5 is used to select the source of the digital audio
transmitter’s system clock. Figure 9 shows the header block
with descriptions for each of the four options. Regardless of
the source selected, the rate will be 128 f
S
.
FIGURE 9. Digital Audio Transmitter Source Selection.
JP3
DIR
512
384
256
LRCK generated by digital audio receiver
LRCK from crystal oscillator/divider, system clock = 512 f
S
LRCK from crystal oscillator/divider, system clock = 384 f
S
LRCK from crystal oscillator/divider, system clock = 256 f
S
JP4
384 f
S
256/512 f
S
When using the crystal oscillator/divider, selects 384 f
S
clock
When using the crystal oscillator/divider, selects 256 f
S
clock
or 512
f
S
clock
JP6 is used to select the polarity of the bit clock (BCK) used
for the digital audio transmitter. Figure 10 shows the header
block with descriptions for the two available options.
FIGURE 10. Digital Audio Transmitter BCK Polarity
Selection.
JP6
INV
NML
Inverted
Normal or non-inverted
CS8412
Analog
Output
DEM-PCM
Evaluation
Board
2nd-Order
Post LPF
SYSCLK
LRCK
BCK
Data
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