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參數(shù)資料
| 型號： | DDC114YH-7 |
| 廠商： | DIODES INC |
| 元件分類： | 功率晶體管 |
| 英文描述： | NPN PRE-BIASED SMALL SIGNAL SOT-563 DUAL SURFACE MOUNT TRANSISTOR |
| 中文描述： | 70 mA, 50 V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR |
| 封裝： | GREEN, PLASTIC PACKAGE-6 |
| 文件頁數(shù)： | 18/30頁 |
| 文件大?。?/td> | 389K |
| 代理商： | DDC114YH-7 |
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SBAS255A JUNE 2004 REVISED NOVEMBER 2004
www.ti.com
18
t
12
T
INT
T
INT
t
16
t
12
t
13
t
15
t
17
Release
State
End Integration Side A
Start Integration Side B
End Integration Side B
Wait State
Side A
Data Ready
Side B
Data Ready
Start Integration Side A
Start Integration Side A
CONV
A/D Conversion
Input 1 and 2
A/D Conversion
Input 3 and 4
DVALID
Figure 14. Conversion Detail for the Internal Operation of the Non-Continuous Mode with Side A
Integrated First
Table 8. Internal Timing for the DDC114 in the Non-Continuous Mode
SYMBOL
DESCRIPTION
CLK = 4MHz, CLK_4X = 0
CLK = 4.8MHz, CLK_4X = 0
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
T
INT
t
12
t
13
Integration Time (non-continuous mode)
A/D Conversion Time (internally controlled)
A/D Conversion Reset Time (internally controlled)
Integrator and A/D Conversion Reset Time
(internally controlled)
Total A/D Conversion and Reset Time (internally controlled)
Release Time
400
1,000,000
320
1,000,000
μ
s
μ
s
μ
s
169.5
4
141.25
3.333
t
15
19.5
16.25
μ
s
t
16
t
17
725.25
±
0.25
604.375
±
0.208
μ
s
μ
s
18
15
t
12
T
INT
T
INT
t
16
t
12
t
13
t
15
t
17
CONV
A/D Conversion
Input 1
A/D Conversion
Input 2
DVALID
Release
State
End Integration Side B
Start Integration Side A
End Integration Side A
Wait State
Side B
Data Ready
Side A
Data Ready
Start Integration Side B
Start Integration Side B
Figure 15. Internal Operation Timing Diagram of the Non-Continuous Mode with Side B Integrated First
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| DDC114YU | 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:NPN PRE-BIASED SMALL SIGNAL SOT-363 DUAL SURFACE MOUNT TRANSISTOR |
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