參數(shù)資料
型號： DDC114EH
廠商： Diodes Inc.
英文描述： NPN PRE-BIASED SMALL SIGNAL SOT-563 DUAL SURFACE MOUNT TRANSISTOR
中文描述： npn型預(yù)偏置信號小的SOT - 563雙表面貼裝晶體管
文件頁數(shù)： 25/30頁
文件大?。?/td> 389K
代理商： DDC114EH
""#
SBAS255A JUNE 2004 REVISED NOVEMBER 2004
www.ti.com
25
RETRIEVAL
BEFORE
AND
AFTER
CONV
TOGGLES (CONTINUOUS MODE)
For the absolute maximum time for data retrieval, data can
be retrieved
before and after
CONV toggles. Nearly all of
T
INT
is available for data retrieval. Figure 25 illustrates
how this is done by combining the two previous methods.
You must pause the retrieval during CONV toggling must
be paused to prevent digital noise, as discussed
previously, and finish before the next data is ready. The
maximum number of DDC114s that can be daisy-chained
together with FORMAT = high is:
T
INT
20 s
80
DCLK
1.75 s
NOTE: 64
τ
DCLK
is for FORMAT = low.
For T
INT
= 400
μ
s and DCLK = 10MHz, the maximum
number of DDC114s is 47 (or 59 for FORMAT = low).
RETRIEVAL: NONCONTINUOUS MODE
Retrieving in noncontinuous mode is slightly different as
compared with the continuous mode. As illustrated in
Figure 26 and described in detail in Application Bulletin
SBAA024 (located at www.ti.com), DVALID goes low in
time t
30
after the first integration completes. If T
INT
is
shorter than this time, all of t
31
is available to retrieve data
before the other side data is ready. For T
INT
> t
30
, the first
integration data is ready before the second integration
completes. Data retrieval must be delayed until the second
integration completes, leaving less time available for
retrieval. The time available is t
31
– (T
INT
– t
30
). The
second integration’s data must be retrieved before the next
round of integration begins. This time is highly dependent
on the pattern used to generate CONV. As with the
continuous mode, data retrieval must halt before and after
CONV toggles (t
28
, t
29
) and be completed before new data
is ready (t
26
).
SYMBOL
DESCRIPTION
CLK = 4MHZ, CLK_4X = 0
MIN
TYP
1.75
10
10
CLK = 4.8MHZ, CLK_4X = 0
MIN
TYP
1.458
10
10
UNITS
MAX
MAX
t26
t28
t29
Hold Time that DOUT is Valid Before Falling Edge of DVALID
Data Retrieval Shutdown Before Edge of CONV
Data Retrieval Start-Up After Edge of CONV
μ
s
μ
s
μ
s
Figure 25. Readback
Before and After
CONV Toggles
SYMBOL
DESCRIPTION
CLK = 4MHz, CLK_4X = 0
MIN
TYP
344.75
±
0.25
362.500
CLK = 4.8MHz, CLK_4X = 0
MIN
TYP
287.292
±
0.208
302.083
UNITS
MAX
MAX
t30
t31
1st ncont Mode Data Ready (see SBAA024)
2nd ncont Mode Data Ready (see SBAA024)
μ
s
μ
s
Figure 26. Readback in Non-Continuous Mode
…
…
…
…
…
…
…
…
…
…
…
…
DCLK
DVALID
CONV
DOUT
Side B
Data
Side A
Data
T
INT
t
29
t
28
t
26
T
INT
T
INT
…
…
…
…
T
INT
T
INT
t
30
T
INT
T
INT
t
31
Side A
Data
Side B
Data
CONV
DVALID
DCLK
DOUT
相關(guān)PDF資料
PDF描述
DDC114EH-7 NPN PRE-BIASED SMALL SIGNAL SOT-563 DUAL SURFACE MOUNT TRANSISTOR
DDC114YK-7 NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR
DDC114EK-7 NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR
DDC114TK-7 NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR
DDC114YH-7 NPN PRE-BIASED SMALL SIGNAL SOT-563 DUAL SURFACE MOUNT TRANSISTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DDC114EH-7 功能描述:開關(guān)晶體管 - 偏壓電阻器 150MW 10K RoHS:否 制造商:ON Semiconductor 配置: 晶體管極性:NPN/PNP 典型輸入電阻器: 典型電阻器比率: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 直流集電極/Base Gain hfe Min:200 mA 最大工作頻率: 集電極—發(fā)射極最大電壓 VCEO:50 V 集電極連續(xù)電流:150 mA 峰值直流集電極電流: 功率耗散:200 mW 最大工作溫度: 封裝:Reel
DDC114EH-7-F 制造商:Diodes Incorporated 功能描述:TRANS DGTL BJT NPN 100MA 6PIN SOT-563 - Tape and Reel
DDC114EK 制造商:DIODES 制造商全稱:Diodes Incorporated 功能描述:NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR
DDC114EK-7 制造商:Diodes Incorporated 功能描述:TRANS DGTL BJT NPN 100MA 6PIN SOT-26 - Tape and Reel
DDC114EK-7-F 制造商:Diodes Incorporated 功能描述:PREBIASED TRANSISTOR SOT-26 R1=R2 NPN 300MW 10KOHMS 10KOHMS - Tape and Reel
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