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參數(shù)資料
| 型號： | DAC8801IDGKRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 0.5 us SETTLING TIME, 14-BIT DAC, PDSO8 |
| 封裝： | 3 X 5 MM, GREEN, PLASTIC, MSOP-8 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 629K |
| 代理商： | DAC8801IDGKRG4 |
www.ti.com
t(CSS)
t(DS)
t(DH)
t(CH)
t(CL)
t(CSH)
SDI
CLK
CS
D13
D12
D11
D10
D9
D8
D7
D6
D1
D0
SLAS403B – NOVEMBER 2004 – REVISED FEBRUARY 2007
Figure 19. DAC8801 Timing Diagram
Table 1. Control Logic Truth Table(1)
CLK
CS
Serial Shift Register
DAC Register
X
H
No effect
Latched
↑+
L
Shift register data advanced one bit
Latched
X
H
No effect
Latched
X
↑+
Shift register data transferred to DAC register
New data loaded from serial register
(1)
↑+ Positive logic transition; X = Don't care
Table 1. Serial Input Register Data Format, Data Loaded MSB First
B13
B0
Bit
(MSB)
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
(LSB)
Data(1)
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(1)
A full 16-bit data word can be loaded into the serial register, but only the last 14 bits are transferred to the DAC register when CS goes
high.
9
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