參數(shù)資料
型號: DAC8801IDGKRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 0.5 us SETTLING TIME, 14-BIT DAC, PDSO8
封裝: 3 X 5 MM, GREEN, PLASTIC, MSOP-8
文件頁數(shù): 15/20頁
文件大?。?/td> 629K
代理商: DAC8801IDGKRG4
www.ti.com
PIN ASSIGNMENTS
1
8
CLK
CS
DRB PACKAGE
(TOP VIEW)
VDD
4
CLK
DGK PACKAGE
(TOP VIEW)
SDI
RFB
VREF
VDD
IOUT
GND
RFB
SDI
VREF
CS
IOUT
GND
3
2
1
5
6
7
8
7
6
5
2
3
4
SLAS403B – NOVEMBER 2004 – REVISED FEBRUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
V
DD = 2.7 V to 5.5 V; IOUT = Virtual GND, GND = 0 V; VREF = 10 V; TA = Full Operating Temperature; all specifications -40°C
to 85
°C unless otherwise noted.
DAC8801
PARAMETER
CONDITIONS
UNITS
MIN
TYP
MAX
Total harmonic distortion
VREF = 5 VPP, Data = 3FFFh, f = 1 kHz
–105
dB
Output spot noise voltage
f = 1 kHz, BW = 1 Hz
12
nV/
√Hz
TERMINAL FUNCTIONS
PIN
NAME
DESCRIPTION
1
CLK
Clock input, positive edge triggered clocks data into shift register
2
SDI
Serial register input, data loads directly into the shift register MSB first. Extra leading bits are ignored.
3
RFB
Internal matching feedback resistor. Connect to external op amp output.
4
VREF
DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance versus code.
5
IOUT
DAC current output. Connects to inverting terminal of external precision I to V op amp.
6
GND
Analog and digital ground
7
VDD
Posiitve power supply input. Specified range of operation 2.7 V to 5.5 V.
Chip select, active low digital input. Transfers shift register data to DAC register on rising edge. See Table 1 for
8
CS
operation.
4
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