參數(shù)資料
型號: DAC8408AT
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: Quad 8-Bit Multiplying CMOS D/A Converter with Memory
中文描述: QUAD, PARALLEL, 8 BITS INPUT LOADING, 0.19 us SETTLING TIME, 8-BIT DAC, CDIP28
封裝: CERDIP-28
文件頁數(shù): 11/16頁
文件大?。?/td> 217K
代理商: DAC8408AT
DAC8408
–11–
REV. A
Figure 7. Quad DAC Bipolar Operation (4-Quadrant Multiplication)
T able II. Bipolar (Offset Binary) Code T able
(Refer to Figure 7)
DAC Data Input
MSB
Analog Output
(DAC A OR DAC B)
LSB
1 1 1 1 1 1 1 1
+V
REF
127
128
1
128
1 0 0 0 0 0 0 1
+V
REF
1 0 0 0 0 0 0 0
0
0 1 1 1 1 1 1 1
–V
REF
1
128
127
128
128
128
0 0 0 0 0 0 0 1
–V
REF
0 0 0 0 0 0 0 0
–V
REF
NOT E
1 LSB = (2
–7
) (V
REF
) =
1
128
(V
REF
)
APPLICAT ION HINT S
General Ground Management:
AC or transient voltages be-
tween AGND and DGND can appear as noise at the DAC8408’s
analog output. Note that in Figures 5 and 6, I
OUT 2A
/I
OUT 2B
and
I
OUT 2C
/I
OUT 2D
are connected to AGND. T herefore, it is rec-
ommended that AGND and DGND be tied together at the
DAC8408 socket. In systems where AGND and DGND are tied
together on the backplane, two diodes (1N914 or equivalent)
should be connected in inverse parallel between AGND and
DGND.
Write E nable T iming:
During the period when both
DS
and
R/
W
are held low, the DAC latches are transparent and the ana-
log output responds directly to the digital data input. T o pre-
vent unwanted variations of the analog output, the R/
W
should
not go low until the data bus is fully settled (DAT A VALID).
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