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參數(shù)資料
| 型號(hào)： | DAC650KL |
| 英文描述： | 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 12位500MHz的數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 98K |
| 代理商： | DAC650KL |
DAC650
9
(2) An external V
BB
system reference is applied to pin 1.
This technique may allow data threshold levels to track
the system over supply and temperature variations.
(3) The internal tracking ECL threshold reference (pin 67) is
applied to pin 1. The output of the tracking ECL
threshold reference is simply the average of two exter-
nally applied levels. These levels are a system logic low
(pin 65) and system logic high (pin 66). This technique
may provide increased noise margin for systems with
levels slightly different from ECL. Leave pins 65-67
open if this option is not used.
TIMING
The DAC650 has an internal edge triggered latch. The
output changes on the positive edge of CLK. This master-
slave latching will assure that the 12 bits will arrive at the bit
switches with a minimum of data skew. Data must have
adequate setup and hold time for proper operation (refer to
Figure 4). Note that the Hold time is negative. Therefore the
data may change before the rising edge of clock and still be
valid.
The DAC650 has a differential ECL clock input. This clock
input can also be driven by a single-ended clock if desired
by tying the CLK input to an external voltage of –1.3V.
Using a true differential clock provides much improved
digital feedthrough immunity, however.
DATA IN/VOUT CORRESPONDENCE
The each full scale output of the DAC650 may be modeled
as either
±
20mA current source in parallel with 50
or a
±
1V voltage source in series with 50
. The nominal current
and voltage bit weights are given in Table I and the input
code vs output voltage relationships are given in Table II.
Transmission line techniques at the output are also recom-
mended to minimize ringing and glitching. Ideally, both of
the outputs should see the same termination, including any
delay between the DAC650 and the load.
Since the outputs V
OUT
and V
OUT
are equal in magnitude but
opposite in sign, they are ideal for driving RF
transformers (Figures 5). The primary may be connected
between the two outputs. The secondary may be floating or
referenced to ground. This results in a 2X signal power and
some cancellation of clock feedthrough, glitching, and
distortion. Figures 6 and 7 give recommended output
amplifiers.
FIGURE 4. Timing Diagram for the DAC650.
Clock 1
t
PWL
Data 1
V
OUT
1
t
P
CLK
Data
V
OUT
t
P
t
SU
t
H
t
PWL
Propagation delay. 50% of CLK to 50% of V
OUT
.
Setup time DATA must remain stable before CLK.
Hold time DATA must remain stable after CLK.
CLK pulse width low (50% to 50%).
SYMBOL
DESCRIPTION
MIN
1.5
1.8
–600
TYP
MAX
ns
ns
ps
ns
UNITS
t
H
t
SU
2.0
–500
1.0
Clock 0
Clock 2
Data 2
Data 0
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