參數(shù)資料
型號： DAC650KL
英文描述： 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER
中文描述： 12位500MHz的數(shù)字模擬轉(zhuǎn)換器
文件頁數(shù)： 2/11頁
文件大?。?/td> 98K
代理商： DAC650KL
DAC650
2
SPECIFICATIONS
ELECTRICAL
Over full specified temperature range, using the internal +10V reference and rated supplies, unless otherwise noted.
DAC650JL
DAC650KL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
TEMPERATURE RANGE
Specification: DAC650JL, KL
(1)
θ
CA
θ
JC
DIGITAL INPUTS
Logic
Resolution
ECL Logic Input Levels
(2)
: V
IL
Ambient
0
+70
*
*
°
C
27
13
*
*
°
C/W
°
C/W
12 Parallel Input Lines
ECL Compatible
12
–2
10
–0.6
10
–1.4
*
*
*
*
*
*
Bits
V
μ
A
V
μ
A
V
Logic “0”
–1.475
–1.8
1.0
–0.8
1.0
–1.3
*
*
*
*
*
*
I
IL
V
IH
I
IH
Logic “1”
–1.115
*
Logic Threshold Voltage
–1.2
*
DIGITAL TIMING
Input Data Rate
CLK Pulse Width Low
Set-Up Time
Hold Time (Referred to CLK)
Propagation Delay
DC
1.0
2.0
–500
500
*
*
*
*
*
MHz
ns
ns
ps
ns
1.8
–600
1.5
*
*
*
ANALOG OUTPUT
Bipolar Output Current
Bipolar Output Voltage
Output Resistance
Output Resistance Drift
Output Capacitance
R
L
= 0
R
L
=
∞
±
20
±
1.0
50
50
5
*
*
*
*
*
mA
V
V
OUT
, V
OUT
to Ground
49
51
*
*
ppm/
°
C
pF
TRANSFER CHARACTERISTICS
Integral Linearity Error
Differential Linearity Error
Best Fit Straight Line
+25
°
C
Over Temperature
±
0.018
±
0.018
±
0.018
Typical
±
0.5
±
0.5
±
0.036
±
0.036
±
0.036
±
0.012
±
0.08
±
0.012
Guaranteed
±
0.5
±
0.25
±
0.024
±
0.024
±
0.024
%FSR
%FSR
%FSR
Monotonicity
Bipolar Gain Error
Bipolar Offset Error
Output Voltage, R
L
=
∞
Output Voltage, R
L
=
∞
±
1.0
±
1.0
±
1.0
±
0.5
%FSR
%FSR
TIME DOMAIN PERFORMANCE
Glitch Energy
Output Rise Time
Output Fall Time
Settling Time
(3)
:
±
0.1%FSR
Major Carry
10% to 90%
90% to 10%
20
300
350
2.0
*
*
*
*
pV-s
ps
ps
ns
Major Carry, 1LSB Change
REFERENCES
V
BB
Input Range (Pin 1)
V
BB INT
Reference (Pin 68)
V
Tracking Reference (Pin 67) ECL
HI IN
= –0.8V, ECL
LO IN
= –1.8V
Internal
Reference
Voltage
(Ref
Out)
Ref in Resistance
Ref in Operating Voltage Range
–1.4
–1.4
–1.4
9.95
–1.3
–1.3
–1.3
10
4950
10.0
–1.2
–1.2
–1.2
10.05
*
*
*
*
*
*
*
*
*
*
*
*
*
*
V
V
V
V
V
4.5
11.0
*
*
DYNAMIC PERFORMANCE
Spurious Free Dynamic Range
(4)
f
O
= 1MHz, f
CLK
= 100MHz
f
O
= 10MHz, f
CLK
= 100MHz
f
O
= 30MHz, f
CLK
= 200MHz
f
O
= 80MHz, f
CLK
= 200MHz
f
O
= 80MHz, f
CLK
= 500MHz
f
= 100MHz, f
CLK
= 500MHz
Output Noise
+25
°
C, Span = DC to f
CLK
/2
+25
°
C, Span = DC to f
CLK
/2
+25
°
C, Span = DC to f
CLK
/2
+25
°
C, Span = DC to f
/2
+25
°
C, Span = DC to 150MHz
+25
°
C, Span = 50MHz to 150MHz
Full Scale Sine Wave Output
65
59
50
47
49
51
68
63
52
50
55
56
1.0
68
62
53
50
52
54
70
65
56
52
58
59
*
dBc
(5)
dBc
dBc
dBc
dBc
dBc
μ
V/ Hz
POWER SUPPLIES
Supply Voltages: +V
CC
Operating, T
MIN
to T
MAX
+14.25
–15.75
+4.75
–5.46
+15
–15
+5
–5.2
0.05
10
–47
53
–191
2.0
+15.75
–14.25
+5.25
–4.94
0.08
13
–50
57
–245
2.6
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
V
V
V
V
–V
CC
+V
DD1
–V
Power Supply Rejection
Supply Currents: +I
CC
All Supplies,
±
5% Change
Operating
%/%
mA
mA
mA
mA
W
–I
CC
+I
DD1
–I
DD2
Power Consumption
Operating
NOTE: (1) Extended temperature range devices are available, inquire. (2) V
(Pin 1) connected to V
(Pin 68). (3) Settling time is influenced by load due to
fast edge speeds. Use good transmission line techniques for best results. (4) Spurious Free Dynamic Range includes both harmonic and non-harmonic related spurs
in the bandwidth indicated. (5) dBc is “dB referred to the fundamental amplitude.”
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