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參數(shù)資料
| 型號： | DAC650KL |
| 英文描述： | 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 12位500MHz的數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 98K |
| 代理商： | DAC650KL |
DAC650
10
If only one output is used, the unused output should be
terminated identically. If the terminations cannot be identi-
cal and the unused output must be unterminated, the termi-
nation for the used output should be as close as possible to
the DAC650.
LAYOUT AND POWER SUPPLIES
A multilayer PC board with a solid ground and power planes
is recommended. An example of a typical circuit configura-
tion is given in Figures 8. The DAC650 has multiple ground
pins to minimize pin impedances. All of the ground pins
(analog and digital both) should be connected directly to the
analog ground plane at the DAC650.
Wide busses for the power paths are recommended as good
general practice. There are several internal power supply
bypass capacitors, but external bypassing is still recom-
mended. A 10
μ
F tantalum capacitor in parallel with a
0.01
μ
F chip capacitor will be sufficient in most applications.
Pin 64, Analog V
EE
, should be connected to the same supply
as the digital V
EE
pins (–5.2V).
MAXIMIZING PERFORMANCE
The DAC650 has been designed to give a very clean analog
output with minimal noise, overshoot, and ringing. In addi-
tion to optimizing the layout and ground of the DAC650,
there are other important issues to consider when optimizing
the performance of this DAC in various AC applications.
The DAC650 includes an internal 50
output impedance to
simplify output interfacing to a 50
load. Because some
loads may be a complex impedance, care must be taken to
match the output impedance with the load. Mismatching of
impedances can cause reflections which will affect the
measured AC performance parameters such as settling time,
harmonic distortion, rise/fall times, etc. Often complex im-
pedances can be matched by placing a variable 3 to 10pF
capacitor at the output of the DAC to ground. Also, probing
the output can present a complex impedance.
The typical performance curves of Spurious Free Dynamic
Range vs various combinations of clock rate and/or input
frequency should give a general idea of the spectral perfor-
mance of the DAC under system specific clock and output
frequencies. We have defined Spurious Free Dynamic Range
as any harmonic or non-harmonic spurs in the indicated
bandwidth . In phase lock loop applications, the harmonics
often fall outside the loop bandwidth of the PLL. In these
cases, as well as cases where the output is filtered, Spurious
BIT
VOLTAGE (No External Load)
CURRENT
1
2
3
4
5
6
7
8
9
10
11
1V
.5V
0.25V
0.125V
62.5mV
31.25mV
15.625mV
7.8125mV
3.9063mV
1.9531mV
976
μ
V
488
μ
V
20mA
10mA
5mA
2.5mA
1.25mA
625
μ
A
312.5
μ
A
156.25
μ
A
78.125
μ
A
39.06
μ
A
19.53
μ
A
9.76
μ
A
12 (LSB)
TABLE I. Nominal Bit Weight Values.
TABLE II. Input Code vs Output Voltage Relationships.
INPUT BITS OUTPUT VOLTAGES
1 2 3 4 5 6 7 8 9 10 11 12
OUT
NV
OUT
–1 + 488
μ
V
–1 + 976
μ
V
–1 + 1.464mV
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0
0
0
0
0
1
0
1
0
+1.000
+1 – 488
μ
V
+1 – 976
μ
V
0 1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0
0
1
0
0
1
0
0
1
0.50
0.000
–0.50 + 488
μ
V
+488
μ
V
+1.000
–1 + 488
μ
V
FIGURE 5. Using an RF Transformer at the Output of the
DAC650. Filtering the Outputs Before the
Transformer Improves the Performance in Some
Applications.
DAC650
V
OUT
39
40
41
45
46
47
V
OUT
Load
Mini Circuits
TT5-1A
FIGURE 6. A High Speed Single Ended Amplifier at the
Output. The Gain is –R
F
/50
.
DAC650
V
OUT
39
40
41
45
46
47
V
OUT
OPA64X
or
OPA600
FIGURE 7. A High Speed Differential Amplifier at the
Output.
DAC650
V
OUT
39
40
41
45
46
47
V
OUT
OPA64X
or
OPA600
R
F
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