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參數(shù)資料
| 型號： | DAC5674IPHPG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 37/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 400MSPS 48-HTQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | CommsDAC™ |
| 設(shè)置時間： | 20ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 550mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-HTQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 400M |
| 配用： | 296-30860-ND - EVAL MODULE FOR DAC5674 |
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DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
7
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
37, 41, 44
I
Analog ground return
AVDD
45, 46
I
Analog supply voltage
BIASJ
40
O
Full-scale output current bias
CLK
29
I
External clock input
CLKC
30
I
Complementary external clock input
CLKGND
31
I
Ground return for internal clock buffer
CLKVDD
32
I
Internal clock buffer supply voltage
D[13..0]
316
I
Data bits 0 through 13
D13 is most significant data bit (MSB)
D0 is least significant data bit (MSB)
DIV[1..0]
27,28
I
PLL prescaler divide ratio settings
DGND
1, 2, 19, 24
I
Digital ground return
DVDD
21, 47, 48
I
Digital supply voltage
EXTIO
39
I/O
Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
Used as internal reference output when EXTLO = AGND, requires a 0.1-
F decoupling capacitor to AGND
when used as reference output
EXTLO
38
I
For internal reference connect to AGND. Connect to AVDD to disable the internal reference
HP1
17
I
Filter 1 high-pass setting. Active high
HP2
18
I
Filter 2 high-pass setting. Active high
IOGND
20
I
Input digital ground return
IODVDD
22
I
Input digital supply voltage
IOUT1
43
O
DAC current output. Full scale when all input bits are set 1
IOUT2
42
O
DAC complementary current output. Full scale when all input bits are 0
LPF
35
I
PLL loop filter connection
PLLGND
33
I
Ground return for internal PLL
PLLLOCK
25
O
PLL lock status bit. PLL is locked to input clock when high. Provides output clock equal to the data rate
when the PLL is disabled.
PLLVDD
34
I
Internal PLL supply voltage. Connect to PLLGND to disable PLL clock multiplier.
RESET
26
I
Reset internal registers. Active high
SLEEP
36
I
Asynchronous hardware power-down input. Active high. Internally pull down.
X4
23
I
4
× interpolation mode. Active high. Filter 1 is bypassed when connected to DGND
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC5674IPHP-ND | 制造商: 功能描述: 制造商:undefined 功能描述: |
| DAC5674IPHPR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14-Bit 400 CommsDAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC5674IPHPRG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14-Bit 400 CommsDAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC5675 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:14-BIT, 400-MSPS DIGITAL-TO-ANALOG CONVERTER |
| DAC5675A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:14-Bit, 400MSPS Digital-to-Analog Converter |
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