參數(shù)資料
型號(hào)： DAC5674IPHPG4
廠商： Texas Instruments
文件頁(yè)數(shù)： 25/39頁(yè)
文件大小： 0K
描述： IC DAC 14BIT 400MSPS 48-HTQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 250
系列： CommsDAC™
設(shè)置時(shí)間： 20ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 550mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-HTQFP（7x7）
包裝： 托盤
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 400M
配用： 296-30860-ND - EVAL MODULE FOR DAC5674
DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
31
The external loop filter components C1, C2, and R1 are given by choosing Gvco, N = Fvco/Fdata, the loop
phase margin
φd and the loop bandwidth ωd. Except for applications where abrupt clock frequency changes
require a fast PLL lock time, it is suggested that
φd be set to at least 80 degrees for stable locking and
suppression of the phase noise side lobes. Phase margins of 60 degrees or less have occasionally been
sensitive to board layout and decoupling details.
The optimum loop bandwidth
ωd depends on both the VCO phase noise, which is largely a function of Gvco,
and the application. For the foregoing example with Gvco = 210 MHz/V, an
ωd = 1 MHz would be typical, but
lower and higher loop bandwidths may provide better phase-noise characteristics. For a higher Gvco, for
example Gvco = 400 MHz/V, a
ωd ≈ 7 MHz would be typical. However, it is suggested that the customer
experiment with varying the loop bandwidth by at least 1/2
× through 2× to verify the optimum setting.
C1, C2, and R1 are then calculated by the following equations:
C1
+ t1 1– t2
t3
C2
+ t1–t2
t3
R1
+
t32
t1(t3 * t2)
where
t1 +
K
dKvco
w2
d
tan
f
d ) secfd
t2 +
1
w
d tan fd ) secfd
t3 +
tan
f
d ) secfd
w
d
and
charge pump current
:
iqp = 1 mA
vco gain:
Kvco = 2
π × Gvco rad/V
Fvco/Fdata:
N = {2, 4, 8, 16, 32}
phase detector gain:
Kd = iqp
× (2πN)1 A/rad
An Excel
spreadsheet is provided by TI for automatically calculating the values for C1, C2, and R.
Completing the preceding example with
PARAMETER
VALUE
UNIT
Gvco
2.10E+02
MHz/V
ωd
1.00E+00
MHz
N
4
φd
80
degrees
the component values are
C1 (F)
C2 (F)
R (
W)
1.51E08
1.16E10
1.21E+02
As the PLL characteristics are not sensitive to these components, the closest 20% tolerance capacitor and 1%
tolerance resistor values can be used. If the calculation results in a negative value for C2 or an unrealistically
large value for C1, then the phase margin may need to be reduced slightly.
USING PowerPAD DEVICES
A thermal land should be placed on the top and bottom layers of the circuit board. The recommended thermal
land size for this package is 5 mm
× 5 mm, with top and bottom layers connected by 9 vias. A thermal land size
of 3,8 mm
× 3,8 mm (as used on the DAC5674 EVM) is adequate for this device.
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