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參數(shù)資料
| 型號(hào)： | DAC2932PFBTG4 |
| 元件分類： | DAC |
| 英文描述： | DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER |
| 中文描述： | 雙通道12位40MSPS數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 343K |
| 代理商： | DAC2932PFBTG4 |
SBAS279C AUGUST 2003 REVISED OCTOBER 2004
www.ti.com
6
TIMING INFORMATION
t
CP
t
CL
t
DO2
t
DO1
t
S1
t
S2
t
H1
t
H2
t
CH
DAC1 (n
1)
CLK
Data In[D0:D11]
IDAC OUT1
IDAC OUT2
DAC2 (n
1)
DAC2 (n)
DAC2 (n + 1)
DAC1 (n)
DAC1 (n +1)
(n
2)
(n
2)
(n
1)
(n
1)
(n)
(n)
Figure 1. Timing Diagram of I-DAC
TIMING REQUIREMENTS
(1,2)
: I-DAC
PARAMETER
DESCRIPTION
tCP
Clock cycle time (period)
tCL
Clock low time
tCH
Clock high time
tS1
Data setup time, I-DAC1
tS2
Data setup time, I-DAC2
tH1
Data hold time, I-DAC1
tH2
Data hold time, I-DAC2
tDO1(3)
Output delay time, I-DAC1
tDO2(3)
Output delay time, I-DAC2
CS hold time (pulse width)
MIN
TYP
25
MAX
UNIT
ns
10
ns
10
ns
0.5
5
ns
0.5
5
ns
2.2
5
ns
2.2
5
ns
tS1 + tCP
tS2+(tCP/2)
ns
ns
tCP + 3.5
ns
CS to clock rising or falling edge setup time
1.5
ns
μ
s
μ
s
STBY rise time to IOUT
PD fall time to IOUT (I-DAC coming out of power-down mode)
(1)Based on design simulation and characterization; not production tested.
(2)All input signals are specified with tr = tf
≤
2ns (10% to 90% of +VDV) and timed from a voltage level of (VIL + VIH)/2.
(3)Output delay time measured from 50% of rising clock edge to 50% point of full-scale transition.
17
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