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參數(shù)資料
| 型號： | DAC2932PFBTG4 |
| 元件分類： | DAC |
| 英文描述： | DUAL 12-BIT 40MSPS DIGITAL TO ANALOG CONVERTER |
| 中文描述： | 雙通道12位40MSPS數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 343K |
| 代理商： | DAC2932PFBTG4 |
SBAS279C AUGUST 2003 REVISED OCTOBER 2004
www.ti.com
4
ELECTRICAL CHARACTERISTICS: I-DAC (continued)
At TA = TMIN to TMAX (typical values are at TA = 25
°
C), +VA = +3V, +VD = +3V, Update Rate = 40MSPS, IOUTFS = 2mA, RL = 250
, CL
≤
10pF,
GSET = H, and internal reference, unless otherwise noted.
DAC2932
TYP
PARAMETER
UNITS
MAX
MIN
TEST CONDITIONS
Reference
Voltage, VREF
Tolerance
Voltage drift
Output current
Input resistance
Input compliance range
Small-signal bandwidth
Digital Inputs(6)
Logic coding
Logic high voltage, VIH
Logic low voltage, VIL
Logic high current
Logic low current
Input capacitance
Power Supply
Analog supply voltage, +VA, +VAV
Digital supply voltage, +VD, +VDV
Analog supply current, IVA
+1.14
+1.22
±
30
40
10
1
+1.22
0.1
+1.26
V
mV
ppm/
°
C
μ
A
M
V
MHz
External VREF
Straight binary
+3
0
±
1
±
1
5
+2
V
V
μ
A
μ
A
pF
+0.8
2.7
2.7
3
3
3.3
3.3
V
V
fCLOCK = 25MSPS, digital inputs at 0
fCLOCK = 40MSPS, fOUT = 2.2MHz
Standby mode
fCLOCK = 25MSPS, digital inputs at 0
fCLOCK = 40MSPS, fOUT = 2.2MHz
Standby mode, clock off
Standby mode, CS = 0, fCLOCK = 25MSPS
fCLOCK = 25MSPS, digital inputs at 0
fCLOCK = 40MSPS, fOUT = 2.2MHz
Standby mode, fCLOCK = 25MSPS
Power-down mode, clock off, digital inputs at 0
4.7
5.4
0.4
2
4.3
0.02
1.3
20
29
5.5
25
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
μ
W
IVA
IVA
Digital supply current, IVD
lVD
IVD
IVD
Power dissipation, PD(8)
25
PD
PD
PD
7
Thermal resistance
TQFP-48
θ
JA
θ
JC
97.5
20
°
C/W
°
C/W
(1)At output IOUT1, IOUT2, while driving a 250
load, transition from 000h to FFFh.
(2)Measured at fCLOCK = 25MSPS and fOUT = 1.0MHz.
(3)Differential, transformer (n = 4:1) coupled output, RL = 400
.
(4)Differential outputs with a 250
load.
(5)
Nominal fullscale output current is I
OUTFS
(6)Ensured by design and characterization; not production tested.
(7)Gain error to remain
≤
10% FSR over the full compliance range.
(8)Combined power dissipation of I-DAC and V-DAC.
32
I
REF
32
V
REF
R
SET
; with V
REF
1.22V (typ) and R
SET
19.6k
(1%)
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