參數(shù)資料
型號: D80530C
英文描述: Microcontroller
中文描述: 微控制器
文件頁數(shù): 4/4頁
文件大小: 74K
代理商: D80530C
Compact D80530C Microcontroller
3-4
March 21, 2000
Pinout
The pinout of the D80530C core has not been fixed to spe-
cific FPGA I/O, thereby, allowing flexibility with a users
application. Signal names are shown in the block diagram
in Figure 1 and described in Table 3.
Ordering Information
This product is available from the AllianceCORE partner
listed on the first page. Please contact the partner for pric-
ing and more information.
The D80530C core is licensed from Evatronix S.A.
Related Information
High-Speed Microcontroller Data Book
, Dallas
Semiconductor, 1995.
CMOS Single-chip 8-bit Micro controllers
, 1996.
Addendum to the MCS
51 Microcontroller Family
, Intel,
1996.
8-bit Embedded Controllers
, Intel, 1990
Contact:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
Phone:
800-548-4725
URL:http://www.intel.com
Xilinx Programmable Logic
For information on Xilinx programmable logic or develop-
ment system software, contact your local Xilinx sales office,
or:
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Phone:
+1 408-559-7778
Fax:
+1 408-559-7114
URL:
www.xilinx.com
For general Xilinx literature, contact:
Phone:
+1 800-231-3386 (inside the US)
+1 408-879-5017 (outside the US)
literature@xilinx.com
For AllianceCORE specific information, contact:
E-mail:
Phone:
E-mail:
+1 408-879-5381
alliancecore@xilinx.com
URL:www.xilinx.com/products/logicore/alliance/tblpart.htm
Table 3: Core Signal Pinout
Signal
Signal
Direction
Description
Internal Program Memory Interface
Output
Output
Input
ROMADDR[13:0]
Output
ROMOE
Output
ROMDATAI[7:0]
Output
Internal Data Memory Interface
RAMDATAI[7:0]
Input
RAMDATAO[7:0]
Output
RAMADDR[7:0]
Output
RAMOE
Output
RAMWE
Output
External SFR Interface
SFRDATAI[7:0]
Input
SFRDATAO[7:0]
Output
SFRADDR[6:0]
Output
SFROE
Output
SFRWE
Output
Interrupt Service Routine
PFI
Input
ALE
PSEN
EA
Address Latch Enable
Program Store Enable
External Access Enable
Memory Address Bus
Memory Output Enable
Memory Data Bus
RAM Data Bus Input
RAM Data Bus Output
RAM Address Bus
Data Output Enable
Data Write Enable
SFR Data Bus Input
SFR Data Bus Output
SFR Address Bus
SFR Output Enable
SFR Write Enable
Power Failure Interrupt
Ports
Input
Port0 Input Bus
Input
Port1 Input Bus
Input
Port2 Input Bus
Input
Port3 Input Bus
Output
Port0Output Bus
Output
Port1 Output Bus
Output
Port2 Output Bus
Output
Port3 Output Bus
Clock_Control
Input
Clock Input
Input
Chip Reset Input
P0i[7:0]
P1i[7:0]
P2i[7:0]
P3i[7:0]
P0o[7:0]
P1o[7:0]
P2o[7:0]
P3o[7:0]
CLK
RESET
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