
March 21, 2000
3-3
CAST, Inc.
Core Engine
The D80530C core engine is composed of four compo-
nents:
Memory control unit
RAM_SFR control unit
Control unit
Arithmetic Logic Unit (ALU)
The D80530C engine allows to fetch instruction from pro-
gram memory and executes them using RAM or SFR.
Memory Control Unit
Can address up to 64K bytes of External Program
Memory Space
Can address up to 64K bytes of External Data Memory
Space
Control Unit
The Control Unit performs instruction fetch and execution
from the Memory Control Unit and the RAM_SFR Control
Unit.
RAM_SFR Control Unit
Can address up to 256 bytes of Read/Write Data
Memory Space
Serves as Interface for off-core Special Function
Registers
Arithmetic Logic Unit (ALU)
The ALU performs:
8-bit arithmetic operations
8-bit logical operations
Boolean manipulations
8 x 8 bit multiplication
8 / 8 bit division
Timer_0 _1
This block has two timers: Timer_0 and Timer_1, which are
nearly identical. Both have four modes:
13-bit Timer/counter
16-bit Timer/counter
8-bit timer/counter with auto reload
Two 8-bit timers (Timer_0 only)
Each timer can also serve as a counter of external pulses
(1 to 0 transition) on the corresponding T0 or T1 pin. The
T0 and T1 pins are input through signals of the P3i bus of
the Ports block. The user can gate the timer/counter using
an external control signal. This allows the timer to measure
the pulse width of external signals.
Interrupt Service Routine
The D80530C core provides a three-priority interrupt sys-
tem. There are 14 interrupt sources. Each source has an
independent priority bit, flag, interrupt vector, and enable.
In addition, interrupts can be globally enabled or disabled.
Ports
The D80530C provides four I/O ports. P0 to P3 are 8-bit bi-
directional I/O ports with separated inputs and outputs.
P0 serves as the multiplexed low-order address and data
bus during accesses to external program and data memo-
ries.
P1 serves the special features, such as, external interrupt
inputs, Serial 1 interface, and Timer 2 inputs.
P2 provides the high-order address byte during fetches
from external program memory that use 16-bit addresses.
P3 serves the special features, such as, read and write
strobes for external data memory, Timer_0 and Timer_1
inputs.
Clock_Control
This unit generates the internal synchronous reset signal. It
also contains registers for selecting the clock for the timers
and for programming the length of the external data mem-
ory accesses.
Core Modifications
The D80530C core can be modified to include features
such as:
Three 16-bit Timer/Counters
Two Serial Peripheral Interfaces in full duplex mode
15 bit Programmable Watchdog Timer
32-Bit Fast Multiplication-Division Unit
4x16 Bit Compare/Capture Unit
Real Time Clock
Please contact CAST, Inc. directly for any required modifi-
cations.
Verification Methods
The functionality of the D80530C core was verified by
means of a proprietary hardware modeler. The same stim-
ulus was applied to a hardware model that contained the
original Intel 80C31 and Dallas DS80C320 chips, and the
results compared with the core’s simulation outputs.
Recommended Design
Experience
The user must be familiar with HDL design methodology, as
well as instantiation of Xilinx netlists in a hierarchical design
environment.