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參數(shù)資料
| 型號： | D80530C |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 74K |
| 代理商： | D80530C |
Compact D80530C Microcontroller
3-2
March 21, 2000
General Description
The D80530C is a fast, single-chip, 8-bit microcontroller. It
is a fully functional 8-bit embedded controller that executes
all ASM51 instructions and has the same instruction set as
the 80C51. The D80530C provides software and hardware
interrupts; an interface for serial communications, and a
timer system with auto-reload resources.
The D80530C is a microcode-free design and is strictly
synchronous with positive-edge clocking, a synchronous
reset, and no internal tri-states.
The core architecture eliminates redundant bus states and
implements parallel execution of fetch and execution
phases. Since a cycle is aligned with memory fetch when
possible, most instructions have the same number of
cycles as bytes. The D80530C uses 4 clocks per cycle. This
leads to performance improvement of rate 2.5 (in terms of
MIPS) with respect to the legacy 8051 device working at
the same clock frequency. The legacy 8051 had a 12-clock
architecture.
Table 2 shows the speed advantage of the D80530C over a
standard 8051. A speed advantages of 3 means that the
D80530C performs the same instruction three times faster
than the standard 8051.
Functional Description
The D80530C is a compact version of the D80530 core.
The D80530C core is partitioned into modules as shown in
Figure 1 and described below.
RAM_SFR_CONTROL
MEMORY_CONTROL
CONTROL_UNIT
INSTR
CYCLE
INSTR
CYCLE
CLOCK_CONTROL
INSTR
CYCLE
CLK
RESET
TF0, IE0
TF1, IE1
TIMER_0_1
PORTS
INTERNAL SFR BUS
X9109
PHASE
INSTR
CORE ENGINE
ALE
PSEN
EA
ROMADDR[13:0]
ROMOE
ROMDATAI[7:0]
RAMDATAI[7:0]
RAMDATAO[7:0]
RAMADDR[7:0]
RAMOE
RAMWE
SFRDATAI[7:0]
SFRADATAO[7:0]
SFRADDR[6:0]
SFROE
SFRWE
FETCH
ARITHMETIC LOGIC
UNIT
INTERRUPT
SERVICE
ROUTINE
P0i[7:0]
P1i[7:0]
P2i[7:0]
P3i[7:0]
P0o[7:0]
P1o[7:0]
P2o[7:0]
P3o[7:0]
PFI
FETCH
Figure 1: D80530C Microcontroller Block Diagram
Table 2: Core Speed Average
Speed
Advantage
3
2
2.4
1.5
1
Average: 2.5
1
Notes:
1. The actual speed improvement seen in any system will depend
on the instruction mix
Number
Instructions
53
2
16
38
2
Sum: 111
Number of
Op Codes
160
2
37
54
2
Sum: 255
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