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參數(shù)資料
| 型號： | D2-45157-QR-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 26/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL AMP PWM CTRLR 68QFN |
| 標準包裝： | 3,000 |
| 系列： | D2Audio™ |
| 類型： | D 類 |
| 輸出類型： | 2 通道（立體聲） |
| 在某負載時最大輸出功率 x 通道數(shù)量： | 30W x 2 @ 8 歐姆 |
| 電源電壓： | 9 V ~ 26 V |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN 裸露焊盤（10x10） |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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D2-45057, D2-45157
4
FN6785.0
July 29, 2010
Absolute Maximum Ratings
Thermal Information
Supply Voltage
HVDD[A:D], VDDHV. . . . . . . . . . . . . . . . -0.3V to +28.0V
RVDD, PWMVDD . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V
Input Voltage
Any Input but XTALI . . . . . . . . . . . .-0.3V to RVDD +0.3V
XTALI. . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD +0.3V
Input Current, Any Pin but Supplies . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
68 Ld QFN Package (Notes 5, 6) . .
25
1
Maximum Storage Temperature . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
Recommended Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
High Voltage Supply Voltage,
HVDD[A:D], VDDHV . . . . . . . . . . . . . . . . . . 9.0V to 26.5V
Digital I/O Supply Voltage, PWMVDD . . . . . . . . . . . . . . 3.3V
Core Supply Voltage, CVDD . . . . . . . . . . . . . . . . . . . . 1.8V
Analog Supply Voltage, PLLVDD . . . . . . . . . . . . . . . . . 1.8V
Minimum Load Impedance (HVDD[A:D]
≤24.0V), ZL . . . . 4Ω
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. Absolute Maximum parameters are not tested in production.
Electrical Specifications TA = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
±10%. All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at
147.456MHz with typical audio data traffic.
PARAMETER
TEST
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNIT
Digital Input High Logic Level (Note 8)
VIH
2-
-
V
Digital Input Low Logic Level (Note 8)
VIL
--
0.8
V
High Level Output Drive Voltage
(IOUT at -Pin Drive Strength Current)
VOH
RVDD - 0.4
-
V
Low Level Output Drive Voltage
(IOUT at +Pin Drive Strength Current)
VOL
--
0.4
V
High Level Input Drive Voltage XTALI Pin
VIHX
0.7
-
PLLVDD
V
Low Level Input Drive Voltage XTALI Pin
VILX
--
0.3
V
Input Leakage Current (Note 9)
IIN
--
±10
A
Input Capacitance
Cin
-
9
-
pF
Output Capacitance
All Outputs Except
OUT[A:D]
Cout
-
9
-
pF
OUT[A:D]
-
190
-
pF
nRESET Pulse Width
tRST
-10
-
ns
Internal Pull-Up Resistance to PWMVDD
(for nERROR0-3, OCFG, nPDN)
--
100
-
kΩ
Digital I/O Supply Pin Voltage, Current
RVDD
and
PWMVDD
33.3
3.6
V
Active Current
-
10
-
mA
Power-Down Current
-
0.01
-
mA
Core Supply Pins
CVDD
1.7
1.8
1.9
V
Active Current
-
300
-
mA
Power-Down Current
(Note 10)
-6
-
mA
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