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參數(shù)資料
| 型號： | CYW2330 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 諧振器 |
| 英文描述： | Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers |
| 中文描述： | DUAL PRESCALER, PDSO20 |
| 封裝： | 0.173 INCH, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 228K |
| 代理商： | CYW2330 |
CYW2330
PRELIMINARY
Document #: 38-07239 Rev. **
Page 7 of 13
Notes:
6.
7.
The MSB is loaded in first.
Low count ratios may violate frequency limits of the phase detector.
Table 2. Shift Register Configuration
[6]
1
2
3
4
Reference Counter and Configuration Bits
R2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CNT1 CNT2
R1
R3
R4
R5
R6
R7
R8
R9
R10 R11 R12 R13 R14 R15
FC
IDO
TS
LD
FO
Programmable Counter bits
CNT1 CNT2
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11 PRE PD
Bit(s) Name
CNT1, CNT2
R1
–
R15
FC
IDO
TS
LD
Function
Control Bits:
Directs programming data to PLL1 (high frequency) or PLL2 (low frequency).
Reference Counter Setting Bits:
15 bits, R = 3 to 32767.
[7]
Phase Sense of the Phase Detector:
Set to match the VCO polarity, H = + (Positive VCO transfer function).
Charge Pump Setting Bit:
ID
O
HIGH = 3.8 mA, ID
O
LOW = 1 mA at V
P
= 3V.
Hi-Impedance State Bit:
Makes D
O
Hi-Impedance for PLL1 and PLL2 when HIGH.
Lock Detect:
Directs the lock detect signal source pin 10. Pin 10 is HIGH with narrow low excursions when
locked. When not locked, this pin is LOW.
Frequency Out:
This bit can be set to read out reference or programmable divider at the LD pin for test
purposes.
Prescaler Divide Bit:
For PLL1: LOW = 32/33 and HIGH = 64/65. For PLL2: LOW = 8/9 and HIGH = 16/17.
Power-down:
LOW = power-up and HIGH = power-down. F
IN
is at a high-impedance state, respective B
counter is disabled, forces D
O
outputs to Hi-Impedance and phase comparators are disabled. The reference
counter is disabled and the OSC input is high-impedance after both PLLs are powered down. Data can be
input and latched in the power-down state.
Swallow Counter Divide Ratio:
A = 0 to 63 for PLL1 and 0 to 15 for PLL2.
Programmable Counter Divide Ratio:
B = 3 to 2047.
[7]
FO
PRE
PD
A1
–
A7
B1
–
B11
Table 3. F
O
/LD Pin Truth Table
FO (Bit 22)
PLL1
0
0
0
0
0
1
0
1
1
1
1
LD (Bit 21)
F
O
/LD Pin Output State
PLL2
0
0
0
0
1
0
1
0
1
1
1
PLL1
0
0
1
1
X
X
X
X
0
1
1
PLL2
0
1
0
1
0
0
1
1
1
0
1
Disable
PLL2 Lock Detect
PLL1 Lock Detect
PLL1/PLL2 Lock Detect
PLL2 Reference Divider Output
PLL1 Reference Divider Output
PLL2 Programmable Divider Output
PLL1 Programmable Divider Output
PLL2 Counter Reset
PLL1 Counter Reset
PLL1/PLL2 Counter Reset
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