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參數(shù)資料
| 型號： | CYW15G0403DXB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, BGA-256 |
| 文件頁數(shù)： | 19/45頁 |
| 文件大?。?/td> | 517K |
| 代理商： | CYW15G0403DXB-BGXC |
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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 19 of 45
“JTAG Support” on page 24
for JTAG state machine initial-
ization.
See
Table 9 on page 20
for the initialize values of the
configuration latches.
Following a device reset, it is necessary to enable the transmit
and receive channels used for normal operation. This can be
done by sequencing the appropriate values on the device
configuration interface.
[5]
Output Bus
Each receive channel presents an 11-signal output bus
consisting of
an 8-bit data bus
a 3-bit status bus.
The signals present on this output bus are modified by the
present operating mode of the CYP(V)(W)15G0403DXB as
selected by the DECBYPx configuration latch. This mapping
is shown in
Table 7
.
When the 10B/8B decoder is bypassed, the framed 10-bit
value is presented to the associated Output Register, along
with a status output signal indicating if the character in the
Output Register is one of the selected framing characters. The
bit usage and mapping of the external signals to the raw 10B
transmission character is shown in
Table 8
.
The COMDETx status output operates the same regardless of
the bit combination selected for character framing by the
FRAMCHARx latch. COMDETx is HIGH when the character in
the output register contains the selected framing character at
the proper character boundary, and LOW for all other bit
combinations.
When the low-latency framer and half-rate receive port
clocking are also enabled, the framer stretches the recovered
clock to the nearest 20-bit boundary such that the rising edge
of RXCLKx+ occurs when COMDETx is present on the
associated output bus.
When the Cypress or Alternate Mode Framer is enabled and
half-rate receive port clocking is also enabled, the output clock
is not modified when framing is detected, but a single pipeline
stage may be added or subtracted from the data stream by the
framer logic such that the rising edge of RXCLKx+ occurs
when COMDETx is present on the associated output bus.
This adjustment only occurs when the framer is enabled.
When the framer is disabled, the clock boundaries are not
adjusted, and COMDETx may be asserted during the rising
edge of RXCLKx– (if an odd number of characters were
received following the initial framing).
Receive Status Bits
When the 10B/8B decoder is enabled, each character
presented at the Output Register includes three associated
status bits. These bits are used to identify
if the contents of the data bus are valid,
the type of character present,
the state of receive BIST operations,
character violations.
These conditions often overlap; e.g. a valid data character
received with incorrect running disparity is not reported as a
valid data character. It is instead reported as a decoder
violation of some specific type. This implies a hierarchy or
priority level to the various status bit combinations. The
hierarchy and value of each status are listed in
Table 11
.
A second status mapping, listed in
Table 11
, is used when the
receive channel is configured for BIST operation. This status
is used to report receive BIST status and progress.
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the RXSTx[2:0]
bits identify the present state of the BIST compare operation.
The BIST state machine has multiple states, as shown in
Figure 2
and
Table 11
. When the receive PLL detects an
out-of-lock condition, the BIST state is forced to the
Start-of-BIST state, regardless of the present state of the BIST
state machine. If the number of detected errors ever exceeds
the number of valid matches by greater than 16, the state
machine is forced to the WAIT_FOR_BIST state where it
monitors the receive path for the first character of the next
BIST sequence (D0.0). Also, if the Elasticity Buffer ever hits an
overflow/underflow condition, the status is forced to the
Table 7. Output Register Bit Assignments
Signal Name
BYPASS ACTIVE
(DECBYPx = 0)
COMDETx
DOUTx[0]
DOUTx[1]
DOUTx[2]
DOUTx[3]
DOUTx[4]
DOUTx[5]
DOUTx[6]
DOUTx[7]
DOUTx[8]
DOUTx[9]
DECODER
(DECBYP = 1)
RXSTx[2]
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
RXSTx[2] (LSB)
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7] (MSB)
Table 8. Decoder Bypass Mode
Signal Name
RXSTx[2] (LSB)
RXSTx[1]
RXSTx[0]
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7] (MSB)
Bus Weight
COMDETx
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
10 Bit Name
a
b
c
d
e
i
f
g
h
j
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