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參數(shù)資料
| 型號： | CYW15G0403DXB-BGXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, LEAD FREE, BGA-256 |
| 文件頁數(shù)： | 17/45頁 |
| 文件大?。?/td> | 517K |
| 代理商： | CYW15G0403DXB-BGXC |
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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 17 of 45
new serial stream and frame to the incoming character bound-
aries.
Deserializer/Framer
Each CDR circuit extracts bits from the associated serial data
stream and clocks these bits into the Shifter/Framer at the
bit-clock rate. When enabled, the Framer examines the data
stream looking for one or more COMMA or K28.5 characters
at all possible bit positions. The location of this character in the
data stream is used to determine the character boundaries of
all following characters.
Framing Character
The CYP(V)(W)15G0403DXB allows selection of different
framing characters on each channel. Two combinations of
framing characters are supported to meet the requirements of
different interfaces. The selection of the framing character is
made through the FRAMCHARx latches via the configuration
interface.
The specific bit combinations of these framing characters are
listed in
Table 6
. When the specific bit combination of the
selected framing character is detected by the framer, the
boundaries of the characters present in the received data
stream are known.
Framer
The framer on each channel operates in one of three different
modes. Each framer may be enabled or disabled using the
RFENx latches via the configuration interface. When the
framer is disabled (RFENx = 0), no combination of received
bits alters the frame information.
When the Low-Latency framer is selected (RFMODEx[1:0] =
00), the framer operates by stretching the recovered character
clock until it aligns with the received character boundaries. In
this mode the framer starts its alignment process on the first
detection of the selected framing character. To reduce the
impact on external circuits that use the recovered clock, the
clock period is not stretched by more than two bit-periods in
any one clock cycle. When operated with a character-rate
output clock, the output of properly framed characters may be
delayed by up to nine character-clock cycles from the
detection of the selected framing character. When operated
with a half-character-rate output clock, the output of properly
framed characters may be delayed by up to 14 character-clock
cycles from the detection of the framing character.
Note
.
When Receive BIST is enabled on a channel, the
Low-Latency Framer must not be enabled. The BIST
sequence contains an aliased K28.5 framing character, which
causes the Receiver to update its character boundaries incor-
rectly.
When RFMODEx[1:0] = 10, the Cypress-Mode Multi-Byte
framer is selected. The required detection of multiple framing
characters makes the associated link much more robust to
incorrect framing due to aliased SYNC characters in the data
stream. In this mode, the framer does not adjust the character
clock boundary, but instead aligns the character to the already
recovered character clock. This ensures that the recovered
clock does not contain any significant phase changes or hops
during normal operation or framing, and allows the recovered
clock to be replicated and distributed to other external circuits
or components using PLL-based clock distribution elements.
In this framing mode the character boundaries are only
adjusted if the selected framing character is detected at least
twice within a span of 50 bits, with both instances on identical
10-bit character boundaries.
When RFMODEx[1:0] = 01, the Alternate-mode Multi-Byte
Framer is enabled. Like the Cypress-mode Multi-Byte Framer,
multiple framing characters must be detected before the
character boundary is adjusted. In this mode, the data stream
must contain a minimum of four of the selected framing
characters, received as consecutive characters, on identical
10-bit boundaries, before character framing is adjusted.
10B/8B Decoder Block
The decoder logic block performs two primary functions:
decoding the received transmission characters to Data and
Special Character codes
comparing generated BIST patterns with received
characters to permit at-speed link and device testing.
The framed parallel output of each deserializer shifter is
passed to its associated 10B/8B Decoder where, if the
decoder is enabled, the input data is transformed from a 10-bit
transmission character back to the original Data or Special
Character code. This block uses the 10B/8B decoder patterns
in
Table 15 on page 39
and
Table 16 on page 43
.
Received
Special Code characters are decoded using
Table 16
. Valid
data characters are indicated by a 000b bit-combination on the
associated RXSTx[2:0] status bits, and Special Character
codes are indicated by a 001b bit-combination of these status
outputs. Framing characters, Invalid patterns, disparity errors,
and synchronization status are presented as alternate combi-
nations of these status bits.
When DECBYPx = 0, the 10B/8B decoder is bypassed via the
configuration interface. When bypassed, raw 10-bit characters
are passed through the receiver and presented at the
RXDx[7:0] and the RXSTA[1:0] outputs as 10-bit wide
characters.
When the decoder is enabled by setting DECBYPx = 1 via the
configuration interface, the 10-bit transmission characters are
decoded using
Table 15
and
Table 16
. Received Special
characters are decoded using
Table 16
. The columns used in
Table 16
are determined by the DECMODEx latch via the
device configuration interface. When DECMODEx = 0 the
ALTERNATE table is used and when DECMODEx = 1 the
CYPRESS table is used.
Table 6. Framing Character Selector
FRAMCHARx
Bits detected in framer
Character Name
COMMA+
COMMA–
–K28.5
+K28.5
Bits Detected
00111110XX
[9]
or 11000001XX
0011111010 or
1100000101
0
1
Note
9. The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the eighth
bit as an inversion of the seventh bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.
[+] Feedback
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