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參數(shù)資料
| 型號： | CYW15G0403DXB-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, BGA-256 |
| 文件頁數(shù)： | 14/45頁 |
| 文件大?。?/td> | 517K |
| 代理商： | CYW15G0403DXB-BGC |
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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 14 of 45
Character encoding rules listed in
Table 16 on page 43
. When
directed to encode the character as a Data character, it is
encoded using the Data Character encoding rules in
Table 15
on page 39
.
The 8B/10B encoder is standards compliant with ANSI/NCITS
ASC X3.230-1994 Fibre Channel, IEEE 802.3z Gigabit
Ethernet, the IBM
ESCON
and FICON channels, ETSI
DVB-ASI, and ATM Forum standards for data transport.
Many of the Special Character codes listed in
Table 16
may be
generated by more than one input character. The
CYP(V)(W)15G0403DXB is designed to support two
independent (but non-overlapping) Special Character code
tables. This allows the CYP(V)(W)15G0403DXB to operate in
mixed environments with other Cypress HOTLink devices
using the enhanced Cypress command code set, and the
reduced command sets of other non-Cypress devices. Even
when used in an environment that normally uses non-Cypress
Special Character codes, the selective use of Cypress
command codes can permit operation where running disparity
and error handling must be managed.
Following conversion of each input character from eight bits to
a 10-bit transmission character, it is passed to the Transmit
Shifter and is shifted out LSB first, as required by ANSI and
IEEE standards for 8B/10B coded serial data streams.
Transmit Modes
Encoder Bypass
When the Encoder is bypassed, the character captured from
the TXDx[7:0] and TXCTx[1:0] input register is passed directly
to the transmit shifter without modification. With the encoder
bypassed, the TXCTx[1:0] inputs are considered part of the
data character and do not perform a control function that would
otherwise modify the interpretation of the TXDx[7:0] bits. The
bit usage and mapping of these control bits when the Encoder
is bypassed is shown in
Table 2
.
When the encoder is enabled, the TXCTx[1:0] data control bits
control the interpretation of the TXDx[7:0] bits and the
characters generated by them. These bits are interpreted as
listed in
Table 3
.
Table 3. Transmit Modes
Word Sync Sequence
When TXCTx[1:0] = 11, a 16-character sequence of K28.5
characters, known as a Word Sync Sequence, is generated on
the associated channel. This sequence of K28.5 characters
may start with either a positive or negative disparity K28.5 (as
determined by the current running disparity and the 8B/10B
coding rules). The disparity of the second and third K28.5
characters in this sequence are reversed from what normal
8B/10B coding rules would generate. The remaining K28.5
characters in the sequence follow all 8B/10B coding rules. The
disparity of the generated K28.5 characters in this sequence
follow a pattern of either ++––+–+–+–+–+–+– or
––++–+–+–+–+–+–+.
The generation of this sequence, once started, cannot be
stopped until all 16 characters have been sent. The content of
the associated input registers are ignored for the duration of
this sequence. At the end of this sequence, if the TXCTx[1:0]
= 11 condition is sampled again, the sequence restarts and
remains uninterruptible for the following 15 character clocks.
Transmit BIST
Each transmit channel contains an internal pattern generator
that can be used to validate both the link and device operation.
These generators are enabled by the associated TXBISTx
latch via the device configuration interface. When enabled, a
register in the associated transmit channel becomes a
signature pattern generator by logically converting to a Linear
Feedback Shift Register (LFSR). This LFSR generates a
511-character (or 526-character) sequence that includes all
Data and Special Character codes, including the explicit
violation symbols. This provides a predictable yet
pseudo-random sequence that can be matched to an identical
LFSR in the attached Receiver(s).
A device reset (RESET sampled LOW) presets the BIST
Enable Latches to disable BIST on all channels.
All data and data-control information present at the associated
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is
active on that channel. If the receive channels are configured
for reference clock operation, each pass is preceded by a
16-character Word Sync Sequence to allow Elasticity Buffer
alignment and management of clock-frequency variations.
Transmit PLL Clock Multiplier
Each Transmit PLL Clock Multiplier accepts a character-rate
or half-character-rate external clock at the associated
REFCLKx± input, and that clock is multiplied by 10 or 20 (as
selected by TXRATEx) to generate a bit-rate clock for use by
the transmit shifter. It also provides a character-rate clock used
by the transmit paths, and outputs this character rate clock as
TXCLKOx.
Table 2. Encoder Bypass Mode
Signal Name
TXDx[0] (LSB)
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXCTx[0]
TXCTx[1] (MSB)
Bus Weight
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
10B Name
a
[7]
b
c
d
e
i
f
g
h
j
TXCTx[1]
0
0
1
1
TXCTx[0]
0
1
0
1
Characters Generated
Encoded data character
K28.5 fill character
Special character code
16-character Word Sync Sequence
[+] Feedback
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| CYW15G0403DXB-BGI | 功能描述:電信線路管理 IC Quad Indep CH XCVR IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYW15G0403DXB-BGXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYW15G0403DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYW15GO403DXB-BGI | 制造商:Cypress Semiconductor 功能描述: |
| CYW170-01SXC | 功能描述:時鐘緩沖器 133MHz Clock RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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